arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node

The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:

../arch/arm64/boot/dts/rockchip/rk3562.dtsi:1115.20-1181.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property

Move the pinctrl node outside and adapt the indentation.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250518220449.2722673-7-heiko@sntech.de

diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
index 292e82ec5d4548ce68dced781f3d31bfd7ed3893..def504ffa3263629cb39fc52c822bd2eba556d17 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -218,6 +218,74 @@
                };
        };
 
+       pinctrl: pinctrl {
+               compatible = "rockchip,rk3562-pinctrl";
+               rockchip,grf = <&ioc_grf>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               gpio0: gpio@ff260000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff260000 0x0 0x100>;
+                       clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 0 32>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio1: gpio@ff620000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff620000 0x0 0x100>;
+                       clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 32 32>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio2: gpio@ff630000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff630000 0x0 0x100>;
+                       clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 64 32>;
+                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio3: gpio@ffac0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xffac0000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 96 32>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
+               };
+
+               gpio4: gpio@ffad0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xffad0000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 128 32>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #gpio-cells = <2>;
+                       #interrupt-cells = <2>;
+               };
+       };
+
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
@@ -1111,74 +1179,6 @@
                        #io-channel-cells = <1>;
                        status = "disabled";
                };
-
-               pinctrl: pinctrl {
-                       compatible = "rockchip,rk3562-pinctrl";
-                       rockchip,grf = <&ioc_grf>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
-
-                       gpio0: gpio@ff260000 {
-                               compatible = "rockchip,gpio-bank";
-                               reg = <0x0 0xff260000 0x0 0x100>;
-                               clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
-                               gpio-controller;
-                               gpio-ranges = <&pinctrl 0 0 32>;
-                               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-                               interrupt-controller;
-                               #gpio-cells = <2>;
-                               #interrupt-cells = <2>;
-                       };
-
-                       gpio1: gpio@ff620000 {
-                               compatible = "rockchip,gpio-bank";
-                               reg = <0x0 0xff620000 0x0 0x100>;
-                               clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
-                               gpio-controller;
-                               gpio-ranges = <&pinctrl 0 32 32>;
-                               interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                               interrupt-controller;
-                               #gpio-cells = <2>;
-                               #interrupt-cells = <2>;
-                       };
-
-                       gpio2: gpio@ff630000 {
-                               compatible = "rockchip,gpio-bank";
-                               reg = <0x0 0xff630000 0x0 0x100>;
-                               clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
-                               gpio-controller;
-                               gpio-ranges = <&pinctrl 0 64 32>;
-                               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                               interrupt-controller;
-                               #gpio-cells = <2>;
-                               #interrupt-cells = <2>;
-                       };
-
-                       gpio3: gpio@ffac0000 {
-                               compatible = "rockchip,gpio-bank";
-                               reg = <0x0 0xffac0000 0x0 0x100>;
-                               clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
-                               gpio-controller;
-                               gpio-ranges = <&pinctrl 0 96 32>;
-                               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                               interrupt-controller;
-                               #gpio-cells = <2>;
-                               #interrupt-cells = <2>;
-                       };
-
-                       gpio4: gpio@ffad0000 {
-                               compatible = "rockchip,gpio-bank";
-                               reg = <0x0 0xffad0000 0x0 0x100>;
-                               clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
-                               gpio-controller;
-                               gpio-ranges = <&pinctrl 0 128 32>;
-                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                               interrupt-controller;
-                               #gpio-cells = <2>;
-                               #interrupt-cells = <2>;
-                       };
-               };
        };
 };