drm/msm/adreno: Drop fictional address_space_size

Really the only purpose of this was to limit the address space size to
4GB to avoid 32b rollover problems in 64b pointer math in older sqe fw.
So replace the address_space_size with a quirk limiting the address
space to 4GB.  In all other cases, use the SMMU input address size (IAS)
to determine the address space size.

v2: Properly account for vm_start

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/649467/

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..f85b7e89bafbfec3f3bc4fd88f53ec5fa586e2ce 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -681,6 +681,7 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_SQE] = "a630_sqe.fw",
                },
                .gmem = (SZ_128K + SZ_4K),
+               .quirks = ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .init = a6xx_gpu_init,
                .zapfw = "a610_zap.mdt",
@@ -713,6 +714,7 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a630_gmu.bin",
                },
                .gmem = SZ_512K,
+               .quirks = ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .init = a6xx_gpu_init,
                .zapfw = "a615_zap.mdt",
@@ -743,7 +745,8 @@ static const struct adreno_info a6xx_gpus[] = {
                },
                .gmem = SZ_512K,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .init = a6xx_gpu_init,
                .zapfw = "a615_zap.mbn",
                .a6xx = &(const struct a6xx_info) {
@@ -769,7 +772,8 @@ static const struct adreno_info a6xx_gpus[] = {
                },
                .gmem = SZ_512K,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .init = a6xx_gpu_init,
                .a6xx = &(const struct a6xx_info) {
                        .protect = &a630_protect,
@@ -791,6 +795,7 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a619_gmu.bin",
                },
                .gmem = SZ_512K,
+               .quirks = ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .init = a6xx_gpu_init,
                .zapfw = "a615_zap.mdt",
@@ -815,6 +820,7 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a619_gmu.bin",
                },
                .gmem = SZ_512K,
+               .quirks = ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .init = a6xx_gpu_init,
                .zapfw = "a615_zap.mdt",
@@ -838,8 +844,9 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a619_gmu.bin",
                },
                .gmem = SZ_512K,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
                .init = a6xx_gpu_init,
                .zapfw = "a615_zap.mdt",
                .a6xx = &(const struct a6xx_info) {
@@ -874,7 +881,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020200,
                        .prim_fifo_threshold = 0x00010000,
                },
-               .address_space_size = SZ_16G,
                .speedbins = ADRENO_SPEEDBINS(
                        { 0, 0 },
                        { 137, 1 },
@@ -907,7 +913,6 @@ static const struct adreno_info a6xx_gpus[] = {
                                { /* sentinel */ },
                        },
                },
-               .address_space_size = SZ_16G,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(
                        0x06030001,
@@ -920,8 +925,9 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a630_gmu.bin",
                },
                .gmem = SZ_1M,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
                .init = a6xx_gpu_init,
                .zapfw = "a630_zap.mdt",
                .a6xx = &(const struct a6xx_info) {
@@ -939,8 +945,9 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a640_gmu.bin",
                },
                .gmem = SZ_1M,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
                .init = a6xx_gpu_init,
                .zapfw = "a640_zap.mdt",
                .a6xx = &(const struct a6xx_info) {
@@ -973,7 +980,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020202,
                        .prim_fifo_threshold = 0x00300200,
                },
-               .address_space_size = SZ_16G,
                .speedbins = ADRENO_SPEEDBINS(
                        { 0, 0 },
                        { 1, 1 },
@@ -1000,7 +1006,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020000,
                        .prim_fifo_threshold = 0x00300200,
                },
-               .address_space_size = SZ_16G,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x06060300),
                .family = ADRENO_6XX_GEN4,
@@ -1019,7 +1024,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020200,
                        .prim_fifo_threshold = 0x00300200,
                },
-               .address_space_size = SZ_16G,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x06030500),
                .family = ADRENO_6XX_GEN4,
@@ -1039,7 +1043,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020202,
                        .prim_fifo_threshold = 0x00200200,
                },
-               .address_space_size = SZ_16G,
                .speedbins = ADRENO_SPEEDBINS(
                        { 0,   0 },
                        { 117, 0 },
@@ -1056,8 +1059,9 @@ static const struct adreno_info a6xx_gpus[] = {
                        [ADRENO_FW_GMU] = "a640_gmu.bin",
                },
                .gmem = SZ_2M,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_4GB_VA,
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
-               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
                .init = a6xx_gpu_init,
                .zapfw = "a640_zap.mdt",
                .a6xx = &(const struct a6xx_info) {
@@ -1085,7 +1089,6 @@ static const struct adreno_info a6xx_gpus[] = {
                        .gmu_cgc_mode = 0x00020200,
                        .prim_fifo_threshold = 0x00800200,
                },
-               .address_space_size = SZ_16G,
        }
 };
 DECLARE_ADRENO_GPULIST(a6xx);
@@ -1395,7 +1398,6 @@ static const struct adreno_info a7xx_gpus[] = {
                        .pwrup_reglist = &a7xx_pwrup_reglist,
                        .gmu_cgc_mode = 0x00020000,
                },
-               .address_space_size = SZ_16G,
                .preempt_record_size = 2860 * SZ_1K,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
@@ -1429,7 +1431,6 @@ static const struct adreno_info a7xx_gpus[] = {
                                { /* sentinel */ },
                        },
                },
-               .address_space_size = SZ_16G,
                .preempt_record_size = 4192 * SZ_1K,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */
@@ -1451,7 +1452,6 @@ static const struct adreno_info a7xx_gpus[] = {
                        .gmu_chipid = 0x7050001,
                        .gmu_cgc_mode = 0x00020202,
                },
-               .address_space_size = SZ_256G,
                .preempt_record_size = 4192 * SZ_1K,
        }, {
                .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
@@ -1484,7 +1484,6 @@ static const struct adreno_info a7xx_gpus[] = {
                                { /* sentinel */ },
                        },
                },
-               .address_space_size = SZ_16G,
                .preempt_record_size = 3572 * SZ_1K,
        }
 };

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 242d02d48c0cd0972bb96a960872b73384fe043b..2289fecbbbf14f7ec02227972049d62408c11dc1 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2268,7 +2268,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
                return ERR_CAST(mmu);
 
        return msm_gem_address_space_create(mmu,
-               "gpu", 0x100000000ULL,
+               "gpu", ADRENO_VM_START,
                adreno_private_address_space_size(gpu));
 }
 

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 26db1f4b5fb90930bdbd2f17682bf47e35870936..2348ffb35f7eb73a26da47881901d9111dca1ad9 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -236,14 +236,27 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
 u64 adreno_private_address_space_size(struct msm_gpu *gpu)
 {
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);
+       const struct io_pgtable_cfg *ttbr1_cfg;
 
        if (address_space_size)
                return address_space_size;
 
-       if (adreno_gpu->info->address_space_size)
-               return adreno_gpu->info->address_space_size;
+       if (adreno_gpu->info->quirks & ADRENO_QUIRK_4GB_VA)
+               return SZ_4G;
 
-       return SZ_4G;
+       if (!adreno_smmu || !adreno_smmu->get_ttbr1_cfg)
+               return SZ_4G;
+
+       ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
+
+       /*
+        * Userspace VM is actually using TTBR0, but both are the same size,
+        * with b48 (sign bit) selecting which TTBRn to use.  So if IAS is
+        * 48, the total (kernel+user) address space size is effectively
+        * 49 bits.  But what userspace is control of is the lower 48.
+        */
+       return BIT(ttbr1_cfg->ias) - ADRENO_VM_START;
 }
 
 #define ARM_SMMU_FSR_TF                 BIT(1)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 92caba3584da0400b44a903e465814af165d40a3..a8f4bf416e64fadbd1c61c991db13d539581e324 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -57,6 +57,7 @@ enum adreno_family {
 #define ADRENO_QUIRK_HAS_HW_APRIV              BIT(3)
 #define ADRENO_QUIRK_HAS_CACHED_COHERENT       BIT(4)
 #define ADRENO_QUIRK_PREEMPTION                        BIT(5)
+#define ADRENO_QUIRK_4GB_VA                    BIT(6)
 
 /* Helper for formating the chip_id in the way that userspace tools like
  * crashdec expect.
@@ -104,7 +105,6 @@ struct adreno_info {
        union {
                const struct a6xx_info *a6xx;
        };
-       u64 address_space_size;
        /**
         * @speedbins: Optional table of fuse to speedbin mappings
         *
@@ -578,6 +578,8 @@ static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
               adreno_is_a740_family(gpu);
 }
 
+/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
+#define ADRENO_VM_START 0x100000000ULL
 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
                     uint32_t param, uint64_t *value, uint32_t *len);