arm64: dts: imx8mp: add cpuidle state "cpu-pd-wait"

So far, only WFI is supported on i.MX8mp platform. Add support for
deeper cpuidle state "cpu-pd-wait" that would allow for better power
usage during runtime. This is a port from NXP downstream kernel.

Signed-off-by: Catalin Popescu <catalin.popescu@leica-geosystems.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 3b02c6e2988c184e5067bc73f52801d7a5aa4357..347f8cb1a3ca501c85ae3c9ff879bc94f2fd7ba1 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -47,6 +47,20 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               idle-states {
+                       entry-method = "psci";
+
+                       cpu_pd_wait: cpu-pd-wait {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0010033>;
+                               local-timer-stop;
+                               entry-latency-us = <1000>;
+                               exit-latency-us = <700>;
+                               min-residency-us = <2700>;
+                               wakeup-latency-us = <1500>;
+                       };
+               };
+
                A53_0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
@@ -65,6 +79,7 @@
                        nvmem-cell-names = "speed_grade";
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&cpu_pd_wait>;
                };
 
                A53_1: cpu@1 {
@@ -83,6 +98,7 @@
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&cpu_pd_wait>;
                };
 
                A53_2: cpu@2 {
@@ -101,6 +117,7 @@
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&cpu_pd_wait>;
                };
 
                A53_3: cpu@3 {
@@ -119,6 +136,7 @@
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
+                       cpu-idle-states = <&cpu_pd_wait>;
                };
 
                A53_L2: l2-cache0 {