mtd: rawnand: Translate obscure bitfields into readable macros

Use the BIT() macro instead of defining a 8-digit value.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Link: https://lore.kernel.org/linux-mtd/20200507105241.14299-2-miquel.raynal@bootlin.com

diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 21873168ba4df9c6f1fecde56f7ad2491dfa1531..4b58de842340674652af5a7a54a90bb73b96de1d 100644 (file)
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -129,36 +129,36 @@ enum nand_ecc_algo {
  * features.
  */
 /* Buswidth is 16 bit */
-#define NAND_BUSWIDTH_16       0x00000002
+#define NAND_BUSWIDTH_16       BIT(1)
 /* Chip has cache program function */
-#define NAND_CACHEPRG          0x00000008
+#define NAND_CACHEPRG          BIT(3)
 /*
  * Chip requires ready check on read (for auto-incremented sequential read).
  * True only for small page devices; large page devices do not support
  * autoincrement.
  */
-#define NAND_NEED_READRDY      0x00000100
+#define NAND_NEED_READRDY      BIT(8)
 
 /* Chip does not allow subpage writes */
-#define NAND_NO_SUBPAGE_WRITE  0x00000200
+#define NAND_NO_SUBPAGE_WRITE  BIT(9)
 
 /* Device is one of 'new' xD cards that expose fake nand command set */
-#define NAND_BROKEN_XD         0x00000400
+#define NAND_BROKEN_XD         BIT(10)
 
 /* Device behaves just like nand, but is readonly */
-#define NAND_ROM               0x00000800
+#define NAND_ROM               BIT(11)
 
 /* Device supports subpage reads */
-#define NAND_SUBPAGE_READ      0x00001000
+#define NAND_SUBPAGE_READ      BIT(12)
 
 /*
  * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
  * patterns.
  */
-#define NAND_NEED_SCRAMBLING   0x00002000
+#define NAND_NEED_SCRAMBLING   BIT(13)
 
 /* Device needs 3rd row address cycle */
-#define NAND_ROW_ADDR_3                0x00004000
+#define NAND_ROW_ADDR_3                BIT(14)
 
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
@@ -173,9 +173,9 @@ enum nand_ecc_algo {
  * Position within the block: Each of these pages needs to be checked for a
  * bad block marking pattern.
  */
-#define NAND_BBM_FIRSTPAGE             0x01000000
-#define NAND_BBM_SECONDPAGE            0x02000000
-#define NAND_BBM_LASTPAGE              0x04000000
+#define NAND_BBM_FIRSTPAGE     BIT(24)
+#define NAND_BBM_SECONDPAGE    BIT(25)
+#define NAND_BBM_LASTPAGE      BIT(26)
 
 /* Position within the OOB data of the page */
 #define NAND_BBM_POS_SMALL             5
@@ -183,21 +183,21 @@ enum nand_ecc_algo {
 
 /* Non chip related options */
 /* This option skips the bbt scan during initialization. */
-#define NAND_SKIP_BBTSCAN      0x00010000
+#define NAND_SKIP_BBTSCAN      BIT(16)
 /* Chip may not exist, so silence any errors in scan */
-#define NAND_SCAN_SILENT_NODEV 0x00040000
+#define NAND_SCAN_SILENT_NODEV BIT(18)
 /*
  * Autodetect nand buswidth with readid/onfi.
  * This suppose the driver will configure the hardware in 8 bits mode
  * when calling nand_scan_ident, and update its configuration
  * before calling nand_scan_tail.
  */
-#define NAND_BUSWIDTH_AUTO      0x00080000
+#define NAND_BUSWIDTH_AUTO      BIT(19)
 /*
  * This option could be defined by controller drivers to protect against
  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
  */
-#define NAND_USE_BOUNCE_BUFFER 0x00100000
+#define NAND_USE_BOUNCE_BUFFER BIT(20)
 
 /*
  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
@@ -207,20 +207,20 @@ enum nand_ecc_algo {
  * If your controller already takes care of this delay, you don't need to set
  * this flag.
  */
-#define NAND_WAIT_TCCS         0x00200000
+#define NAND_WAIT_TCCS         BIT(21)
 
 /*
  * Whether the NAND chip is a boot medium. Drivers might use this information
  * to select ECC algorithms supported by the boot ROM or similar restrictions.
  */
-#define NAND_IS_BOOT_MEDIUM    0x00400000
+#define NAND_IS_BOOT_MEDIUM    BIT(22)
 
 /*
  * Do not try to tweak the timings at runtime. This is needed when the
  * controller initializes the timings on itself or when it relies on
  * configuration done by the bootloader.
  */
-#define NAND_KEEP_TIMINGS      0x00800000
+#define NAND_KEEP_TIMINGS      BIT(23)
 
 /* Cell info constants */
 #define NAND_CI_CHIPNR_MSK     0x03