pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration

Modify clkrun and serirq pin configuration on the Nuvoton NPCM8XX BMC
SoC.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/20240716194008.3502068-7-tmaimon77@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index bc947d0d6ede8f9086c99d391ba1120999e63cba..2cc433a74ad286aba95145a1ca9578f7851cc2fc 100644 (file)
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -1485,13 +1485,13 @@ static const struct npcm8xx_pincfg pincfg[] = {
        NPCM8XX_PINCFG(159,     mmc, MFSEL3, 10,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          DSTR(8, 12) | SLEW),
        NPCM8XX_PINCFG(160,     clkout, MFSEL1, 21,     none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          DSTR(8, 12) | SLEW),
        NPCM8XX_PINCFG(161,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
-       NPCM8XX_PINCFG(162,     serirq, MFSEL1, 31,     none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          DSTR(8, 12)),
+       NPCM8XX_PINCFG(162,     clkrun, MFSEL3, 16,     none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          DSTR(8, 12)),
        NPCM8XX_PINCFG(163,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(164,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(165,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(166,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(167,     lpc, MFSEL1, 26,        espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
-       NPCM8XX_PINCFG(168,     none, NONE, 0,          espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
+       NPCM8XX_PINCFG(168,     serirq, MFSEL1, 31,     espi, MFSEL4, 8,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(169,     scipme, MFSEL3, 0,      smb21, MFSEL5, 29,      none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(170,     smi, MFSEL1, 22,        smb21, MFSEL5, 29,      none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),
        NPCM8XX_PINCFG(171,     smb6, MFSEL3, 1,        none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          none, NONE, 0,          0),