[ARM] Convert set_pte_ext implementions to macros
authorRussell King <rmk@dyn-67.arm.linux.org.uk>
Sat, 6 Sep 2008 16:19:08 +0000 (17:19 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 1 Oct 2008 15:40:52 +0000 (16:40 +0100)
There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
18 files changed:
arch/arm/mm/proc-arm1020.S
arch/arm/mm/proc-arm1020e.S
arch/arm/mm/proc-arm1022.S
arch/arm/mm/proc-arm1026.S
arch/arm/mm/proc-arm6_7.S
arch/arm/mm/proc-arm720.S
arch/arm/mm/proc-arm920.S
arch/arm/mm/proc-arm922.S
arch/arm/mm/proc-arm925.S
arch/arm/mm/proc-arm926.S
arch/arm/mm/proc-feroceon.S
arch/arm/mm/proc-macros.S
arch/arm/mm/proc-sa110.S
arch/arm/mm/proc-sa1100.S
arch/arm/mm/proc-v6.S
arch/arm/mm/proc-v7.S
arch/arm/mm/proc-xsc3.S
arch/arm/mm/proc-xscale.S

index 5673f4d6113ba94e7f05954f790489428d4eec8c..453f828f1fbb8b9377512f855bf9924a7a8d1ab2 100644 (file)
@@ -399,29 +399,7 @@ ENTRY(cpu_arm1020_switch_mm)
        .align  5
 ENTRY(cpu_arm1020_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r1, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        mcr     p15, 0, r0, c7, c10, 4
index 4343fdb0e9e55f453129f24b37c41e7d29e56cf8..a226dd330c2d1bcd978d392829fac1c33619aa12 100644 (file)
@@ -383,29 +383,7 @@ ENTRY(cpu_arm1020e_switch_mm)
        .align  5
 ENTRY(cpu_arm1020e_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r1, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
index 2a4ea1659e963321cae90278949cf036c216ae17..68db8c5a4e98609b7964c04e5321fbccf26f275d 100644 (file)
@@ -365,29 +365,7 @@ ENTRY(cpu_arm1022_switch_mm)
        .align  5
 ENTRY(cpu_arm1022_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r1, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
index 77a1babd421c9d6f5c235299632ae57d5e0dc1cf..c02f303d3add506ab43cafa254c8ac70fb853b13 100644 (file)
@@ -354,29 +354,7 @@ ENTRY(cpu_arm1026_switch_mm)
        .align  5
 ENTRY(cpu_arm1026_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r1, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
index c371fc87776ef0c6b7fffdf4f2d7a7f47a1d32d4..5e78c483e48ac0ef57cc89807df8ec6703538143 100644 (file)
@@ -20,6 +20,8 @@
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 ENTRY(cpu_arm6_dcache_clean_area)
 ENTRY(cpu_arm7_dcache_clean_area)
                mov     pc, lr
@@ -214,30 +216,13 @@ ENTRY(cpu_arm7_switch_mm)
  *        : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
-               .align  5
+       .align  5
 ENTRY(cpu_arm6_set_pte_ext)
 ENTRY(cpu_arm7_set_pte_ext)
 #ifdef CONFIG_MMU
-               str     r1, [r0], #-2048                @ linux version
-
-               eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-               bic     r2, r1, #PTE_SMALL_AP_MASK
-               bic     r2, r2, #PTE_TYPE_MASK
-               orr     r2, r2, #PTE_TYPE_SMALL
-
-               tst     r1, #L_PTE_USER                 @ User?
-               orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-               tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-               orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-               tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
-               movne   r2, #0
-
-               str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
 #endif /* CONFIG_MMU */
-               mov     pc, lr
+       mov     pc, lr
 
 /*
  * Function: _arm6_7_reset
index eda733d30455d18bd97bb565d2df8540cd1eb4a4..6d3e0620be71e0cb598dd921c441c4aeed75897e 100644 (file)
@@ -93,29 +93,12 @@ ENTRY(cpu_arm720_switch_mm)
  *        : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
-               .align  5
+       .align  5
 ENTRY(cpu_arm720_set_pte_ext)
 #ifdef CONFIG_MMU
-               str     r1, [r0], #-2048                @ linux version
-
-               eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-               bic     r2, r1, #PTE_SMALL_AP_MASK
-               bic     r2, r2, #PTE_TYPE_MASK
-               orr     r2, r2, #PTE_TYPE_SMALL
-
-               tst     r1, #L_PTE_USER                 @ User?
-               orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-               tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-               orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-               tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young
-               movne   r2, #0
-
-               str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
 #endif
-               mov     pc, lr
+       mov     pc, lr
 
 /*
  * Function: arm720_reset
index 28cdb060df454cf352ac9797092e9d0a8012e3f9..260595bc912bcfa7748f8fab436dffd731acea5b 100644 (file)
@@ -351,33 +351,11 @@ ENTRY(cpu_arm920_switch_mm)
        .align  5
 ENTRY(cpu_arm920_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r2, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-#endif /* CONFIG_MMU */
+#endif
        mov     pc, lr
 
        __INIT
index 94ddcb4a4b76d630f4e94d5048f27bdfb253c04a..0428f77b0d725c0e1bd28222f1e6fe8e1a8a1feb 100644 (file)
@@ -355,29 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
        .align  5
 ENTRY(cpu_arm922_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r2, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
index d045812f33999cc0ef40d03ee95034499fd0cda1..30194781fd0123d436e192118ccd2dbb9bdc797a 100644 (file)
@@ -398,29 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
        .align  5
 ENTRY(cpu_arm925_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r2, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
index 4cd33169a7c917235cd8d549d36a2666c0bc32a5..10e6ac257892ac39d5cb656885dc2a8146a7e616 100644 (file)
@@ -359,29 +359,7 @@ ENTRY(cpu_arm926_switch_mm)
        .align  5
 ENTRY(cpu_arm926_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
-       eor     r3, r2, #0x0a                   @ C & small page?
-       tst     r3, #0x0b
-       biceq   r2, r2, #4
-#endif
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext
        mov     r0, r0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
index f2e5884c513a05f0b0905a9f5c3ee023a8c702f7..240366ee81e82a40514c7fdff2ccb0c555b43998 100644 (file)
@@ -446,24 +446,7 @@ ENTRY(cpu_feroceon_switch_mm)
        .align  5
 ENTRY(cpu_feroceon_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 #if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
index b13150052a76bd6c5d6cc16b17a48d05978c16f8..d1be25313d7b55f0d06fed7d178d7426454fc689 100644 (file)
        mov     \reg, #16                       @ size offset
        mov     \reg, \reg, lsl \tmp            @ actual cache line size
        .endm
+
+
+/*
+ * Sanity check the PTE configuration for the code below - which makes
+ * certain assumptions about how these bits are layed out.
+ */
+#if L_PTE_SHARED != PTE_EXT_SHARED
+#error PTE shared bit mismatch
+#endif
+#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
+#error PTE bufferable bit mismatch
+#endif
+#if L_PTE_CACHEABLE != PTE_CACHEABLE
+#error PTE cacheable bit mismatch
+#endif
+#if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
+     L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
+#error Invalid Linux PTE bit settings
+#endif
+
+/*
+ * The ARMv6 and ARMv7 set_pte_ext translation function.
+ *
+ * Permission translation:
+ *  YUWD  APX AP1 AP0  SVC     User
+ *  0xxx   0   0   0   no acc  no acc
+ *  100x   1   0   1   r/o     no acc
+ *  10x0   1   0   1   r/o     no acc
+ *  1011   0   0   1   r/w     no acc
+ *  110x   0   1   0   r/w     r/o
+ *  11x0   0   1   0   r/w     r/o
+ *  1111   0   1   1   r/w     r/w
+ */
+       .macro  armv6_set_pte_ext
+       str     r1, [r0], #-2048                @ linux version
+
+       bic     r3, r1, #0x000003f0
+       bic     r3, r3, #PTE_TYPE_MASK
+       orr     r3, r3, r2
+       orr     r3, r3, #PTE_EXT_AP0 | 2
+
+       tst     r1, #L_PTE_WRITE
+       tstne   r1, #L_PTE_DIRTY
+       orreq   r3, r3, #PTE_EXT_APX
+
+       tst     r1, #L_PTE_USER
+       orrne   r3, r3, #PTE_EXT_AP1
+       tstne   r3, #PTE_EXT_APX
+       bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+
+       tst     r1, #L_PTE_EXEC
+       orreq   r3, r3, #PTE_EXT_XN
+
+       tst     r1, #L_PTE_YOUNG
+       tstne   r1, #L_PTE_PRESENT
+       moveq   r3, #0
+
+       str     r3, [r0]
+       mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+       .endm
+
+
+/*
+ * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
+ * covering most CPUs except Xscale and Xscale 3.
+ *
+ * Permission translation:
+ *  YUWD   AP  SVC     User
+ *  0xxx  0x00 no acc  no acc
+ *  100x  0x00 r/o     no acc
+ *  10x0  0x00 r/o     no acc
+ *  1011  0x55 r/w     no acc
+ *  110x  0xaa r/w     r/o
+ *  11x0  0xaa r/w     r/o
+ *  1111  0xff r/w     r/w
+ */
+       .macro  armv3_set_pte_ext wc_disable=1
+       str     r1, [r0], #-2048                @ linux version
+
+       eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+
+       bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
+       bic     r2, r2, #PTE_TYPE_MASK
+       orr     r2, r2, #PTE_TYPE_SMALL
+
+       tst     r3, #L_PTE_USER                 @ user?
+       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
+
+       tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
+
+       tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
+       movne   r2, #0
+
+       .if     \wc_disable
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+       tst     r2, #PTE_CACHEABLE
+       bicne   r2, r2, #PTE_BUFFERABLE
+#endif
+       .endif
+       str     r2, [r0]                        @ hardware version
+       .endm
+
+
+/*
+ * Xscale set_pte_ext translation, split into two halves to cope
+ * with work-arounds.  r3 must be preserved by code between these
+ * two macros.
+ *
+ * Permission translation:
+ *  YUWD  AP   SVC     User
+ *  0xxx  00   no acc  no acc
+ *  100x  00   r/o     no acc
+ *  10x0  00   r/o     no acc
+ *  1011  01   r/w     no acc
+ *  110x  10   r/w     r/o
+ *  11x0  10   r/w     r/o
+ *  1111  11   r/w     r/w
+ */
+       .macro  xscale_set_pte_ext_prologue
+       str     r1, [r0], #-2048                @ linux version
+
+       eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+
+       bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
+       orr     r2, r2, #PTE_TYPE_EXT           @ extended page
+
+       tst     r3, #L_PTE_USER                 @ user?
+       orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
+
+       tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+       orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
+                                               @ combined with user -> user r/w
+       .endm
+
+       .macro  xscale_set_pte_ext_epilogue
+       tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
+       movne   r2, #0                          @ no -> fault
+
+       str     r2, [r0]                        @ hardware version
+       mov     ip, #0
+       mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
+       mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
+       .endm
index bbe10576c861d2c6f117fb79e2ae9d1a37fcab2a..df3aebbb55d06595ee4036f79278499f98787e1b 100644 (file)
@@ -153,24 +153,7 @@ ENTRY(cpu_sa110_switch_mm)
        .align  5
 ENTRY(cpu_sa110_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
index 871ba018252e4f5b67360c7722935f56b9f1ee83..8e85e7cbc82f1f5c45b1e77775f2a025d810e47f 100644 (file)
@@ -166,24 +166,7 @@ ENTRY(cpu_sa1100_switch_mm)
        .align  5
 ENTRY(cpu_sa1100_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       bic     r2, r1, #PTE_SMALL_AP_MASK
-       bic     r2, r2, #PTE_TYPE_MASK
-       orr     r2, r2, #PTE_TYPE_SMALL
-
-       tst     r1, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
-
-       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
-
-       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0
-
-       str     r2, [r0]                        @ hardware version
+       armv3_set_pte_ext wc_disable=0
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
index 5702ec58b2a2a9ae8f8e120ad59aabec0c65e049..70c623534021e3477bf6d323fe7e8be641691d90 100644 (file)
@@ -114,46 +114,10 @@ ENTRY(cpu_v6_switch_mm)
  *               (hardware version is stored at -1024 bytes)
  *     - pte   - PTE value to store
  *     - ext   - value for extended PTE bits
- *
- *     Permissions:
- *       YUWD  APX AP1 AP0     SVC     User
- *       0xxx   0   0   0      no acc  no acc
- *       100x   1   0   1      r/o     no acc
- *       10x0   1   0   1      r/o     no acc
- *       1011   0   0   1      r/w     no acc
- *       110x   0   1   0      r/w     r/o
- *       11x0   0   1   0      r/w     r/o
- *       1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v6_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r3, r1, #0x000003f0
-       bic     r3, r3, #0x00000003
-       orr     r3, r3, r2
-       orr     r3, r3, #PTE_EXT_AP0 | 2
-
-       tst     r1, #L_PTE_WRITE
-       tstne   r1, #L_PTE_DIRTY
-       orreq   r3, r3, #PTE_EXT_APX
-
-       tst     r1, #L_PTE_USER
-       orrne   r3, r3, #PTE_EXT_AP1
-       tstne   r3, #PTE_EXT_APX
-       bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-
-       tst     r1, #L_PTE_YOUNG
-       biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
-       tst     r1, #L_PTE_EXEC
-       orreq   r3, r3, #PTE_EXT_XN
-
-       tst     r1, #L_PTE_PRESENT
-       moveq   r3, #0
-
-       str     r3, [r0]
-       mcr     p15, 0, r0, c7, c10, 1 @ flush_pte
+       armv6_set_pte_ext
 #endif
        mov     pc, lr
 
index b49f9a4c82c8e4375f8449bfed5f2527b36598c2..172e2eeb6ddb7e1c30f44eae2b64c6d79d348f2a 100644 (file)
@@ -99,46 +99,10 @@ ENTRY(cpu_v7_switch_mm)
  *               (hardware version is stored at -1024 bytes)
  *     - pte   - PTE value to store
  *     - ext   - value for extended PTE bits
- *
- *     Permissions:
- *       YUWD  APX AP1 AP0     SVC     User
- *       0xxx   0   0   0      no acc  no acc
- *       100x   1   0   1      r/o     no acc
- *       10x0   1   0   1      r/o     no acc
- *       1011   0   0   1      r/w     no acc
- *       110x   0   1   0      r/w     r/o
- *       11x0   0   1   0      r/w     r/o
- *       1111   0   1   1      r/w     r/w
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r3, r1, #0x000003f0
-       bic     r3, r3, #0x00000003
-       orr     r3, r3, r2
-       orr     r3, r3, #PTE_EXT_AP0 | 2
-
-       tst     r1, #L_PTE_WRITE
-       tstne   r1, #L_PTE_DIRTY
-       orreq   r3, r3, #PTE_EXT_APX
-
-       tst     r1, #L_PTE_USER
-       orrne   r3, r3, #PTE_EXT_AP1
-       tstne   r3, #PTE_EXT_APX
-       bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-
-       tst     r1, #L_PTE_YOUNG
-       biceq   r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
-
-       tst     r1, #L_PTE_EXEC
-       orreq   r3, r3, #PTE_EXT_XN
-
-       tst     r1, #L_PTE_PRESENT
-       moveq   r3, #0
-
-       str     r3, [r0]
-       mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+       armv6_set_pte_ext
 #endif
        mov     pc, lr
 
index 7bd9e7197f607773b5fa41bc0fb740f707f3e1b1..ad1ce5a89221c6190d736192417ce4c42f71c5e2 100644 (file)
@@ -349,34 +349,16 @@ ENTRY(cpu_xsc3_switch_mm)
  */
        .align  5
 ENTRY(cpu_xsc3_set_pte_ext)
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r2, r1, #0xff0                  @ keep C, B bits
-       orr     r2, r2, #PTE_TYPE_EXT           @ extended page
-       tst     r1, #L_PTE_SHARED               @ shared?
-       orrne   r2, r2, #0x200
-
-       eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       tst     r3, #L_PTE_USER                 @ user?
-       orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
-
-       tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
-       orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
-                                               @ combined with user -> user r/w
+       xscale_set_pte_ext_prologue
 
        @ If it's cacheable, it needs to be in L2 also.
-       eor     ip, r1, #L_PTE_CACHEABLE
-       tst     ip, #L_PTE_CACHEABLE
-       orreq   r2, r2, #PTE_EXT_TEX(0x5)
+       tst     r1, #L_PTE_CACHEABLE
+       orrne   r2, r2, #PTE_EXT_TEX(0x5)
 
-       tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
-       movne   r2, #0                          @ no -> fault
+       tst     r1, #L_PTE_SHARED               @ shared?
+       orrne   r2, r2, #0x200
 
-       str     r2, [r0]                        @ hardware version
-       mov     ip, #0
-       mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
-       mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
+       xscale_set_pte_ext_epilogue
        mov     pc, lr
 
        .ltorg
index 2dd85273976fcf4aa29e6066ad0975cd4de3582b..8d7512f9cba7906c86c65b1fa3bb985f156cd3c3 100644 (file)
@@ -433,20 +433,7 @@ ENTRY(cpu_xscale_switch_mm)
  */
        .align  5
 ENTRY(cpu_xscale_set_pte_ext)
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r2, r1, #0xff0
-       orr     r2, r2, #PTE_TYPE_EXT           @ extended page
-
-       eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       tst     r3, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
-
-       tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
-                                               @ combined with user -> user r/w
-
+       xscale_set_pte_ext_prologue
        @
        @ Handle the X bit.  We want to set this bit for the minicache
        @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
@@ -456,11 +443,10 @@ ENTRY(cpu_xscale_set_pte_ext)
        @
        @  X = (C & ~W & ~B) | (C & W & B & write_allocate)
        @
-       eor     ip, r1, #L_PTE_CACHEABLE
-       tst     ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
+       and     ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
+       teq     ip, #L_PTE_CACHEABLE
 #if PTE_CACHE_WRITE_ALLOCATE
-       eorne   ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-       tstne   ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
+       teqne   ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
 #endif
        orreq   r2, r2, #PTE_EXT_TEX(1)
 
@@ -474,13 +460,7 @@ ENTRY(cpu_xscale_set_pte_ext)
        teq     ip, #L_PTE_USER | L_PTE_CACHEABLE
        biceq   r2, r2, #PTE_BUFFERABLE
 
-       tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0                          @ no -> fault
-
-       str     r2, [r0]                        @ hardware version
-       mov     ip, #0
-       mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
-       mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
+       xscale_set_pte_ext_epilogue
        mov     pc, lr