clk: rockchip: rk3576: define clk_otp_phy_g

The phy clock of the OTP block is also present, but was not defined
so far. Though its clk-id already existed, so just define its location.

Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210224510.1194963-2-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c
index 595e010341f73aaf7fb0a06d9c6b0864fff0d85b..be703f250197af2097fa591837de03accb8c51da 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3576.c
+++ b/drivers/clk/rockchip/clk-rk3576.c
@@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
                        RK3576_CLKGATE_CON(5), 14, GFLAGS),
        GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
                        RK3576_CLKGATE_CON(5), 15, GFLAGS),
+       GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
+                       RK3576_CLKGATE_CON(6), 0, GFLAGS),
        COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,
                        RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,
                        RK3576_CLKGATE_CON(6), 3, GFLAGS),