Version 1 of the Activity Monitors architecture implements a counter group
of four fixed and architecturally defined 64-bit event counters.
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- CPU cycle counter: increments at the frequency of the CPU.
- Constant counter: increments at the fixed frequency of the system
clock.
Firmware (code running at higher exception levels, e.g. arm-tf) support is
needed to:
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- Enable access for lower exception levels (EL2 and EL1) to the AMU
registers.
- Enable the counters. If not enabled these will read as 0.
The fixed counters of AMUv1 are accessible though the following system
register definitions:
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- SYS_AMEVCNTR0_CORE_EL0
- SYS_AMEVCNTR0_CONST_EL0
- SYS_AMEVCNTR0_INST_RET_EL0
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Currently, access from userspace to the AMU registers is disabled due to:
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- Security reasons: they might expose information about code executed in
secure mode.
- Purpose: AMU counters are intended for system management use.
Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
guest side is disabled due to:
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- Security reasons: they might expose information about code executed
by other guests or the host.