cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map

Name the field @reg_map, because @reg_map->host will be used for
mapping operations beyond component registers (i.e. AER registers).
This is valid for all occurrences of @comp_map. Change them all.

Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-5-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 03bbf36e6fb0fe0e984eae990209b7e45ac58357..f6ced15dbf73670d07f861671c8bb87bdf8936d5 100644 (file)
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -712,7 +712,7 @@ static int cxl_port_setup_regs(struct cxl_port *port,
 {
        if (dev_is_platform(port->uport_dev))
                return 0;
-       return cxl_setup_comp_regs(&port->dev, &port->comp_map,
+       return cxl_setup_comp_regs(&port->dev, &port->reg_map,
                                   component_reg_phys);
 }
 
@@ -729,9 +729,9 @@ static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport,
         * register probing, and fixup @host after the fact, since @host may be
         * NULL.
         */
-       rc = cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map,
+       rc = cxl_setup_comp_regs(dport->dport_dev, &dport->reg_map,
                                 component_reg_phys);
-       dport->comp_map.host = host;
+       dport->reg_map.host = host;
        return rc;
 }
 

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b5b015b661eae4765899d115157e39f32f6191a6..3a51b58a66d0880f09afae6c93da716490158fe6 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -572,7 +572,7 @@ struct cxl_dax_region {
  * @regions: cxl_region_ref instances, regions mapped by this port
  * @parent_dport: dport that points to this port in the parent
  * @decoder_ida: allocator for decoder ids
- * @comp_map: component register capability mappings
+ * @reg_map: component and ras register mapping parameters
  * @nr_dports: number of entries in @dports
  * @hdm_end: track last allocated HDM decoder instance for allocation ordering
  * @commit_end: cursor to track highest committed decoder for commit ordering
@@ -592,7 +592,7 @@ struct cxl_port {
        struct xarray regions;
        struct cxl_dport *parent_dport;
        struct ida decoder_ida;
-       struct cxl_register_map comp_map;
+       struct cxl_register_map reg_map;
        int nr_dports;
        int hdm_end;
        int commit_end;
@@ -620,7 +620,7 @@ struct cxl_rcrb_info {
 /**
  * struct cxl_dport - CXL downstream port
  * @dport_dev: PCI bridge or firmware device representing the downstream link
- * @comp_map: component register capability mappings
+ * @reg_map: component and ras register mapping parameters
  * @port_id: unique hardware identifier for dport in decoder target list
  * @rcrb: Data about the Root Complex Register Block layout
  * @rch: Indicate whether this dport was enumerated in RCH or VH mode
@@ -628,7 +628,7 @@ struct cxl_rcrb_info {
  */
 struct cxl_dport {
        struct device *dport_dev;
-       struct cxl_register_map comp_map;
+       struct cxl_register_map reg_map;
        int port_id;
        struct cxl_rcrb_info rcrb;
        bool rch;