drm/amdgpu: move VM fields into job
authorChristian König <christian.koenig@amd.com>
Fri, 6 May 2016 15:50:03 +0000 (17:50 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 11 May 2016 17:30:31 +0000 (13:30 -0400)
They are the same for all IBs.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
14 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

index 9b55ad35160286aa0ee59872fe686c68cb8d1f70..d4c1eb7816f01c80b3367b575a9796a104c6facd 100644 (file)
@@ -283,7 +283,8 @@ struct amdgpu_ring_funcs {
        int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
        /* command emit functions */
        void (*emit_ib)(struct amdgpu_ring *ring,
-                       struct amdgpu_ib *ib, bool ctx_switch);
+                       struct amdgpu_ib *ib,
+                       unsigned vm_id, bool ctx_switch);
        void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
                           uint64_t seq, unsigned flags);
        void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -741,11 +742,6 @@ struct amdgpu_ib {
        uint64_t                        gpu_addr;
        uint32_t                        *ptr;
        struct amdgpu_user_fence        *user;
-       unsigned                        vm_id;
-       uint64_t                        vm_pd_addr;
-       uint32_t                        gds_base, gds_size;
-       uint32_t                        gws_base, gws_size;
-       uint32_t                        oa_base, oa_size;
        uint32_t                        flags;
        /* resulting sequence number */
        uint64_t                        sequence;
@@ -1262,6 +1258,11 @@ struct amdgpu_job {
        uint32_t                num_ibs;
        void                    *owner;
        uint64_t                ctx;
+       unsigned                vm_id;
+       uint64_t                vm_pd_addr;
+       uint32_t                gds_base, gds_size;
+       uint32_t                gws_base, gws_size;
+       uint32_t                oa_base, oa_size;
        struct amdgpu_user_fence uf;
 };
 #define to_amdgpu_job(sched_job)               \
@@ -2221,7 +2222,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, c) (r)->funcs->emit_ib((r), (ib), (c))
+#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
index 2895d63c9979cf8692d4209eec76cb0d70e58cec..9ab2f0886a148ee415f6480fc66563c45b39dd9c 100644 (file)
@@ -473,6 +473,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
                goto error_validate;
 
        if (p->bo_list) {
+               struct amdgpu_bo *gds = p->bo_list->gds_obj;
+               struct amdgpu_bo *gws = p->bo_list->gws_obj;
+               struct amdgpu_bo *oa = p->bo_list->oa_obj;
                struct amdgpu_vm *vm = &fpriv->vm;
                unsigned i;
 
@@ -481,6 +484,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 
                        p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
                }
+
+               if (gds) {
+                       p->job->gds_base = amdgpu_bo_gpu_offset(gds);
+                       p->job->gds_size = amdgpu_bo_size(gds);
+               }
+               if (gws) {
+                       p->job->gws_base = amdgpu_bo_gpu_offset(gws);
+                       p->job->gws_size = amdgpu_bo_size(gws);
+               }
+               if (oa) {
+                       p->job->oa_base = amdgpu_bo_gpu_offset(oa);
+                       p->job->oa_size = amdgpu_bo_size(oa);
+               }
        }
 
 error_validate:
@@ -744,26 +760,6 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
                j++;
        }
 
-       /* add GDS resources to first IB */
-       if (parser->bo_list) {
-               struct amdgpu_bo *gds = parser->bo_list->gds_obj;
-               struct amdgpu_bo *gws = parser->bo_list->gws_obj;
-               struct amdgpu_bo *oa = parser->bo_list->oa_obj;
-               struct amdgpu_ib *ib = &parser->job->ibs[0];
-
-               if (gds) {
-                       ib->gds_base = amdgpu_bo_gpu_offset(gds);
-                       ib->gds_size = amdgpu_bo_size(gds);
-               }
-               if (gws) {
-                       ib->gws_base = amdgpu_bo_gpu_offset(gws);
-                       ib->gws_size = amdgpu_bo_size(gws);
-               }
-               if (oa) {
-                       ib->oa_base = amdgpu_bo_gpu_offset(oa);
-                       ib->oa_size = amdgpu_bo_size(oa);
-               }
-       }
        /* wrap the last IB with user fence */
        if (parser->job->uf.bo) {
                struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];
index dacbd2e32072b395f844e21d1ae5368a141fbef5..201aceb01d8a8adfbdbcf495262493ab95ced95b 100644 (file)
@@ -74,8 +74,6 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                        ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
        }
 
-       ib->vm_id = 0;
-
        return 0;
 }
 
@@ -147,7 +145,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                return -EINVAL;
        }
 
-       if (vm && !ibs->vm_id) {
+       if (vm && !job->vm_id) {
                dev_err(adev->dev, "VM IB without ID\n");
                return -EINVAL;
        }
@@ -162,10 +160,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                patch_offset = amdgpu_ring_init_cond_exec(ring);
 
        if (vm) {
-               r = amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
-                                   ib->gds_base, ib->gds_size,
-                                   ib->gws_base, ib->gws_size,
-                                   ib->oa_base, ib->oa_size);
+               r = amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr,
+                                   job->gds_base, job->gds_size,
+                                   job->gws_base, job->gws_size,
+                                   job->oa_base, job->oa_size);
                if (r) {
                        amdgpu_ring_undo(ring);
                        return r;
@@ -187,7 +185,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
                        continue;
 
-               amdgpu_ring_emit_ib(ring, ib, need_ctx_switch);
+               amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
+                                   need_ctx_switch);
                need_ctx_switch = false;
        }
 
@@ -197,8 +196,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        r = amdgpu_fence_emit(ring, &hwf);
        if (r) {
                dev_err(adev->dev, "failed to emit fence (%d)\n", r);
-               if (ib->vm_id)
-                       amdgpu_vm_reset_id(adev, ib->vm_id);
+               if (job && job->vm_id)
+                       amdgpu_vm_reset_id(adev, job->vm_id);
                amdgpu_ring_undo(ring);
                return r;
        }
index a0961f2a93d26ccc3d763d6359bfb4567476b558..8ea68d0cfad66dcac037cb9f76c6b704a2a06a67 100644 (file)
@@ -142,23 +142,15 @@ static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
 
        struct fence *fence = amdgpu_sync_get_fence(&job->sync);
 
-       if (fence == NULL && vm && !job->ibs->vm_id) {
+       if (fence == NULL && vm && !job->vm_id) {
                struct amdgpu_ring *ring = job->ring;
-               unsigned i, vm_id;
-               uint64_t vm_pd_addr;
                int r;
 
                r = amdgpu_vm_grab_id(vm, ring, &job->sync,
                                      &job->base.s_fence->base,
-                                     &vm_id, &vm_pd_addr);
+                                     &job->vm_id, &job->vm_pd_addr);
                if (r)
                        DRM_ERROR("Error getting VM ID (%d)\n", r);
-               else {
-                       for (i = 0; i < job->num_ibs; ++i) {
-                               job->ibs[i].vm_id = vm_id;
-                               job->ibs[i].vm_pd_addr = vm_pd_addr;
-                       }
-               }
 
                fence = amdgpu_sync_get_fence(&job->sync);
        }
index ad91664a764953726d8f19aa03bfab543ecdbabc..875626a2eccbd912371e12f4f09e4573521e427c 100644 (file)
@@ -762,7 +762,8 @@ out:
  * @ib: the IB to execute
  *
  */
-void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, bool ctx_switch)
+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
+                            unsigned vm_id, bool ctx_switch)
 {
        amdgpu_ring_write(ring, VCE_CMD_IB);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
index 40d0650e3a3711e2bce783dc3b2a83b5f6f6dc53..f40cf761c66f45f40fe5cf1d42646852d82101fb 100644 (file)
@@ -34,7 +34,8 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
                               bool direct, struct fence **fence);
 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
-void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, bool ctx_switch);
+void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
+                            unsigned vm_id, bool ctx_switch);
 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                unsigned flags);
 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
index 6c2aa2b863b2c3ac101281501efd14825b56f700..518dca43b133a2eaa638031be93c4af9522c5b81 100644 (file)
@@ -210,9 +210,10 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  * Schedule an IB in the DMA ring (CIK).
  */
 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
-                          struct amdgpu_ib *ib, bool ctx_switch)
+                                 struct amdgpu_ib *ib,
+                                 unsigned vm_id, bool ctx_switch)
 {
-       u32 extra_bits = ib->vm_id & 0xf;
+       u32 extra_bits = vm_id & 0xf;
        u32 next_rptr = ring->wptr + 5;
 
        while ((next_rptr & 7) != 4)
index 189ef2b23668336689c8a408eeeffc10e9ecd0d8..7f18a53ab53ac8bc18c992d7fdc76d10a283c3d4 100644 (file)
@@ -2030,7 +2030,8 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
  * on the gfx ring for execution by the GPU.
  */
 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
-                                     struct amdgpu_ib *ib, bool ctx_switch)
+                                     struct amdgpu_ib *ib,
+                                     unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
        u32 next_rptr = ring->wptr + 5;
@@ -2056,7 +2057,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (ib->vm_id << 24);
+       control |= ib->length_dw | (vm_id << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
@@ -2069,7 +2070,8 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 }
 
 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
-                                         struct amdgpu_ib *ib, bool ctx_switch)
+                                         struct amdgpu_ib *ib,
+                                         unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
        u32 next_rptr = ring->wptr + 5;
@@ -2084,7 +2086,7 @@ static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 
        header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (ib->vm_id << 24);
+       control |= ib->length_dw | (vm_id << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
index 0d556c907ab6f8a4a727462f6ee8d8558a196716..92647fbf5b8b44700f4cd5aa4d27b4d0a9c5b428 100644 (file)
@@ -5646,7 +5646,8 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 }
 
 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
-                                     struct amdgpu_ib *ib, bool ctx_switch)
+                                     struct amdgpu_ib *ib,
+                                     unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
        u32 next_rptr = ring->wptr + 5;
@@ -5672,7 +5673,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (ib->vm_id << 24);
+       control |= ib->length_dw | (vm_id << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
@@ -5685,7 +5686,8 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 }
 
 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
-                                         struct amdgpu_ib *ib, bool ctx_switch)
+                                         struct amdgpu_ib *ib,
+                                         unsigned vm_id, bool ctx_switch)
 {
        u32 header, control = 0;
        u32 next_rptr = ring->wptr + 5;
@@ -5701,7 +5703,7 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
 
        header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (ib->vm_id << 24);
+       control |= ib->length_dw | (vm_id << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
index de94adb2b19efe2bf5f499bb0eb3e6a90258d25e..f4c3130d3fdb20eee732b7c4e6e123ca008906a1 100644 (file)
@@ -242,9 +242,10 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  * Schedule an IB in the DMA ring (VI).
  */
 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
-                                  struct amdgpu_ib *ib, bool ctx_switch)
+                                  struct amdgpu_ib *ib,
+                                  unsigned vm_id, bool ctx_switch)
 {
-       u32 vmid = ib->vm_id & 0xf;
+       u32 vmid = vm_id & 0xf;
        u32 next_rptr = ring->wptr + 5;
 
        while ((next_rptr & 7) != 2)
index ca2aee3e88a35b1fbccd03d317b9cfdb75e35849..063f08a9957a1e96ecb82316fe479abe38dfc082 100644 (file)
@@ -400,9 +400,10 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  * Schedule an IB in the DMA ring (VI).
  */
 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
-                                  struct amdgpu_ib *ib, bool ctx_switch)
+                                  struct amdgpu_ib *ib,
+                                  unsigned vm_id, bool ctx_switch)
 {
-       u32 vmid = ib->vm_id & 0xf;
+       u32 vmid = vm_id & 0xf;
        u32 next_rptr = ring->wptr + 5;
 
        while ((next_rptr & 7) != 2)
index a75ffb5b11b251f1f1ec2c1a7be1f30bde8d14c4..f07551476a70db5ba2fd4b7c6c3eb3f87a2889b1 100644 (file)
@@ -489,7 +489,8 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
  * Write ring commands to execute the indirect buffer
  */
 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
-                                 struct amdgpu_ib *ib, bool ctx_switch)
+                                 struct amdgpu_ib *ib,
+                                 unsigned vm_id, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
        amdgpu_ring_write(ring, ib->gpu_addr);
index ecb81014d8369cefc67fad2474a56ac6cacb64d1..e0a76a883d46bab43513df7b3e1b5f9e3cda90dd 100644 (file)
@@ -539,7 +539,8 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
  * Write ring commands to execute the indirect buffer
  */
 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
-                                 struct amdgpu_ib *ib, bool ctx_switch)
+                                 struct amdgpu_ib *ib,
+                                 unsigned vm_id, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
index a43f1a7c58bc8c6be957fa7668bf382d61a586bf..c9929d665c015195837cf1dc587b4e8c5ee371ba 100644 (file)
@@ -631,7 +631,8 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
  * Write ring commands to execute the indirect buffer
  */
 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
-                                 struct amdgpu_ib *ib, bool ctx_switch)
+                                 struct amdgpu_ib *ib,
+                                 unsigned vm_id, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));