Revert "drm/amd/display: Tune min clk values for MPO for RV"

This reverts commit 57eeaf47a613c67d0380cf0afad73d8f52df2670.
Original issue of flash line when MPO enabled on idle screen
was fixed by raising clocks. This had negative effect of extra
power being drained. With the upstream commit 9d03bb102028
("drm/amd/display: disable dcn10 pipe split by default")
flash line issue was fixed and had positive effect for
battery life. Hence this patch is no more required.

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 75b8240ed0595b073af4622a39817e812b81c0c4..e133edc587d318098e5576acbff9f30584f8fe68 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,17 +187,6 @@ static void ramp_up_dispclk_with_dpp(
        clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
 }
 
-static bool is_mpo_enabled(struct dc_state *context)
-{
-       int i;
-
-       for (i = 0; i < context->stream_count; i++) {
-               if (context->stream_status[i].plane_count > 1)
-                       return true;
-       }
-       return false;
-}
-
 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
                        struct dc_state *context,
                        bool safe_to_lower)
@@ -295,22 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
                if (pp_smu->set_hard_min_fclk_by_freq &&
                                pp_smu->set_hard_min_dcfclk_by_freq &&
                                pp_smu->set_min_deep_sleep_dcfclk) {
-                       // Only increase clocks when display is active and MPO is enabled
-                       if (display_count && is_mpo_enabled(context)) {
-                               pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
-                                               ((new_clocks->fclk_khz / 1000) *  101) / 100);
-                               pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
-                                               ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
-                               pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
-                                               (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
-                       } else {
-                               pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
-                                               new_clocks->fclk_khz / 1000);
-                               pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
-                                               new_clocks->dcfclk_khz / 1000);
-                               pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
-                                               (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
-                       }
+                       pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
+                       pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
+                       pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
                }
        }
 }