ARM: dts: at91: at91sam9rl: switch to new sckc bindings

Remove the child nodes of the sckc as they are not necessary anymore.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 6b5777f3c20b66a395feedad0615de6d990f1f6f..c23bb66fee1fc30ab8d3a047bf0c0639baaaba91 100644 (file)
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -869,30 +869,11 @@
                                status = "disabled";
                        };
 
-                       sckc@fffffd50 {
+                       clk32k: sckc@fffffd50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffd50 0x4>;
-
-                               slow_osc: slow_osc {
-                                       compatible = "atmel,at91sam9x5-clk-slow-osc";
-                                       #clock-cells = <0>;
-                                       atmel,startup-time-usec = <1200000>;
-                                       clocks = <&slow_xtal>;
-                               };
-
-                               slow_rc_osc: slow_rc_osc {
-                                       compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
-                                       #clock-cells = <0>;
-                                       atmel,startup-time-usec = <75>;
-                                       clock-frequency = <32768>;
-                                       clock-accuracy = <50000000>;
-                               };
-
-                               clk32k: slck {
-                                       compatible = "atmel,at91sam9x5-clk-slow";
-                                       #clock-cells = <0>;
-                                       clocks = <&slow_rc_osc &slow_osc>;
-                               };
+                               clocks = <&slow_xtal>;
+                               #clock-cells = <0>;
                        };
 
                        rtc@fffffd20 {