phy: ti: gmii-sel: Enable SGMII mode for J784S4

TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20231221102956.754617-1-c-vankar@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 555b323f45da1ee6dc69ef606860786ac5cc16ae..05004c8a758f2b9b63b2fc3284b52c33b58397e3 100644 (file)
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -247,7 +247,7 @@ static const
 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
        .use_of_data = true,
        .regfields = phy_gmii_sel_fields_am654,
-       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) |
+       .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
                       BIT(PHY_INTERFACE_MODE_USXGMII),
        .num_ports = 8,
        .num_qsgmii_main_ports = 2,