The Single Root I/O Virtualization (SR-IOV) extension to
the PCI Express (PCIe) specification suite is supported
starting from 12th generation of Intel Graphics processors.
Add a device flag that we will use to enable SR-IOV specific
code paths and to indicate our readiness to support SR-IOV.
We will enable this flag for the specific platforms once all
required changes and additions will be ready and merged.
Bspec: 52391
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231115073804.1861-1-michal.wajdeczko@intel.com
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
return xe->info.has_flat_ccs;
}
+static inline bool xe_device_has_sriov(struct xe_device *xe)
+{
+ return xe->info.has_sriov;
+}
+
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
#endif
u8 has_llc:1;
/** @has_range_tlb_invalidation: Has range based TLB invalidations */
u8 has_range_tlb_invalidation:1;
+ /** @has_sriov: Supports SR-IOV */
+ u8 has_sriov:1;
/** @enable_display: display enabled */
u8 enable_display:1;
/** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */
u8 has_heci_gscfi:1;
u8 has_llc:1;
+ u8 has_sriov:1;
u8 bypass_mtcfg:1;
u8 supports_mmio_ext:1;
};
}
}
-
static int xe_info_init(struct xe_device *xe,
const struct xe_device_desc *desc,
const struct xe_subplatform_desc *subplatform_desc)
xe->info.graphics_name = graphics_desc->name;
xe->info.media_name = media_desc ? media_desc->name : "none";
xe->info.has_llc = desc->has_llc;
+ xe->info.has_sriov = desc->has_sriov;
xe->info.bypass_mtcfg = desc->bypass_mtcfg;
xe->info.supports_mmio_ext = desc->supports_mmio_ext;
xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size;