iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
- iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
+ iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
iowrite32(0x00000103, pd->regs + XFER_MODE);
iowrite32(0, pd->regs + RETRY_WAIT_CNT);
iowrite32(0, pd->regs + INT_CSR);
#define ODD_DMA_STRIDE 0x24
#define EVEN_PIXEL_FMT 0x30
#define ODD_PIXEL_FMT 0x34
-#define FIFO_TRIGER 0x38
+#define FIFO_TRIGGER 0x38
#define XFER_MODE 0x3C
#define CSR1 0x40
#define RETRY_WAIT_CNT 0x44