drm/msm/dpu: enable CDM_0 for DPUs 1.x - 4.x
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 20 Feb 2025 03:59:24 +0000 (05:59 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Wed, 5 Mar 2025 02:34:13 +0000 (04:34 +0200)
Enable the CDM_0 block on DPU versions 1.x - 4.x as
documented in the vendor dtsi file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/638408/
Link: https://lore.kernel.org/r/20250220-dpu-add-cdm-v2-3-77f5f0df3d9a@linaro.org
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

index ab3dfb0b374ead36c7f07b0a77c703fb2c09ff8a..1f32807bb5e5d49b696832c4eab54c05106bfd4b 100644 (file)
@@ -190,6 +190,7 @@ const struct dpu_mdss_cfg dpu_msm8937_cfg = {
        .mdss_ver = &msm8937_mdss_ver,
        .caps = &msm8937_dpu_caps,
        .mdp = msm8937_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(msm8937_ctl),
        .ctl = msm8937_ctl,
        .sspp_count = ARRAY_SIZE(msm8937_sspp),
index 6bdaecca676144f9162ab1839d99f3e2e3386dc7..42131959ff22020a83c0ea65d79a56fd57c800f9 100644 (file)
@@ -167,6 +167,7 @@ const struct dpu_mdss_cfg dpu_msm8917_cfg = {
        .mdss_ver = &msm8917_mdss_ver,
        .caps = &msm8917_dpu_caps,
        .mdp = msm8917_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(msm8917_ctl),
        .ctl = msm8917_ctl,
        .sspp_count = ARRAY_SIZE(msm8917_sspp),
index 14f36ea6ad0eb61e87f043437a8cd78bb1bde49c..2b4723a5c67606d68dea905d947cd691bb28eda0 100644 (file)
@@ -198,6 +198,7 @@ const struct dpu_mdss_cfg dpu_msm8953_cfg = {
        .mdss_ver = &msm8953_mdss_ver,
        .caps = &msm8953_dpu_caps,
        .mdp = msm8953_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(msm8953_ctl),
        .ctl = msm8953_ctl,
        .sspp_count = ARRAY_SIZE(msm8953_sspp),
index 491f6f5827d151011dd3f74bef2a4b8bf69591ab..5cf19de71f060818d257f95aa781b91ec201d4e4 100644 (file)
@@ -316,6 +316,7 @@ const struct dpu_mdss_cfg dpu_msm8996_cfg = {
        .mdss_ver = &msm8996_mdss_ver,
        .caps = &msm8996_dpu_caps,
        .mdp = msm8996_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(msm8996_ctl),
        .ctl = msm8996_ctl,
        .sspp_count = ARRAY_SIZE(msm8996_sspp),
index 64c94e919a69804599916404dff59fa4a6ac6cff..746474679ef5b9ce7ef351e2d5434706d6109d33 100644 (file)
@@ -302,6 +302,7 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
        .mdss_ver = &msm8998_mdss_ver,
        .caps = &msm8998_dpu_caps,
        .mdp = &msm8998_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(msm8998_ctl),
        .ctl = msm8998_ctl,
        .sspp_count = ARRAY_SIZE(msm8998_sspp),
index 424815e7fb7dd858448bd41b5368b729373035f8..4f2f68b07f203a11529f7a680fb87b448305d80a 100644 (file)
@@ -269,6 +269,7 @@ const struct dpu_mdss_cfg dpu_sdm660_cfg = {
        .mdss_ver = &sdm660_mdss_ver,
        .caps = &sdm660_dpu_caps,
        .mdp = &sdm660_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(sdm660_ctl),
        .ctl = sdm660_ctl,
        .sspp_count = ARRAY_SIZE(sdm660_sspp),
index df01227fc36468f4945c03e767e1409ea4fc0896..c70bef025ac4190347f81d75caf4777786fbeaf7 100644 (file)
@@ -205,6 +205,7 @@ const struct dpu_mdss_cfg dpu_sdm630_cfg = {
        .mdss_ver = &sdm630_mdss_ver,
        .caps = &sdm630_dpu_caps,
        .mdp = &sdm630_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(sdm630_ctl),
        .ctl = sdm630_ctl,
        .sspp_count = ARRAY_SIZE(sdm630_sspp),
index 72bd4f7e9e504c771d999dcf6277fceb169cffca..ab7b4822ca630f8258bc9eb52c0b967e9bc34d18 100644 (file)
@@ -319,6 +319,7 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
        .mdss_ver = &sdm845_mdss_ver,
        .caps = &sdm845_dpu_caps,
        .mdp = &sdm845_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(sdm845_ctl),
        .ctl = sdm845_ctl,
        .sspp_count = ARRAY_SIZE(sdm845_sspp),
index daef07924886a529ee30349ae80375a324bbc245..c2fde980fb521d9259a9f1e3bf88cc81f46fdfe8 100644 (file)
@@ -132,6 +132,7 @@ const struct dpu_mdss_cfg dpu_sdm670_cfg = {
        .mdss_ver = &sdm670_mdss_ver,
        .caps = &sdm845_dpu_caps,
        .mdp = &sdm670_mdp,
+       .cdm = &dpu_cdm_1_x_4_x,
        .ctl_count = ARRAY_SIZE(sdm845_ctl),
        .ctl = sdm845_ctl,
        .sspp_count = ARRAY_SIZE(sdm670_sspp),
index ec7f42a334fc688bec468df490c81a89dd3d396d..a6bb46b201e907566e88abce945507d1bab51b3b 100644 (file)
@@ -507,6 +507,13 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
 /*************************************************************
  * CDM block config
  *************************************************************/
+static const struct dpu_cdm_cfg dpu_cdm_1_x_4_x = {
+       .name = "cdm_0",
+       .id = CDM_0,
+       .len = 0x224,
+       .base = 0x79200,
+};
+
 static const struct dpu_cdm_cfg dpu_cdm_5_x = {
        .name = "cdm_0",
        .id = CDM_0,