arm64/kexec: Test page size support with new TGRAN range values

commit 79d82cbcbb3d2a56c009ad6a6df92c5dee061dad upstream.

The commit 26f55386f964 ("arm64/mm: Fix __enable_mmu() for new TGRAN range
values") had already switched into testing ID_AA64MMFR0_TGRAN range values.
This just changes system_supports_[4|16|64]kb_granule() helpers to perform
similar range tests as well. While here, it standardizes page size specific
supported min and max TGRAN values.

Cc: Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1626237975-1909-1-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 423f9b40e4d951a8403263cf2b7d4d9a40452487..31ba0ac7db63060007b7393b58f6fe38d0412d4e 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -648,7 +648,8 @@ static inline bool system_supports_4kb_granule(void)
        val = cpuid_feature_extract_unsigned_field(mmfr0,
                                                ID_AA64MMFR0_TGRAN4_SHIFT);
 
-       return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;
+       return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_64kb_granule(void)
@@ -660,7 +661,8 @@ static inline bool system_supports_64kb_granule(void)
        val = cpuid_feature_extract_unsigned_field(mmfr0,
                                                ID_AA64MMFR0_TGRAN64_SHIFT);
 
-       return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;
+       return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_16kb_granule(void)
@@ -672,7 +674,8 @@ static inline bool system_supports_16kb_granule(void)
        val = cpuid_feature_extract_unsigned_field(mmfr0,
                                                ID_AA64MMFR0_TGRAN16_SHIFT);
 
-       return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;
+       return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_mixed_endian_el0(void)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 763a745af6a82545080406cc7c63a3d0ea115628..06755fad383047564f673c918e30622871411ba0 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -786,12 +786,16 @@
 #define ID_AA64MMFR0_ASID_SHIFT                4
 #define ID_AA64MMFR0_PARANGE_SHIFT     0
 
-#define ID_AA64MMFR0_TGRAN4_NI         0xf
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED  0x0
-#define ID_AA64MMFR0_TGRAN64_NI                0xf
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
-#define ID_AA64MMFR0_TGRAN16_NI                0x0
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
+#define ID_AA64MMFR0_TGRAN4_NI                 0xf
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN      0x0
+#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX      0x7
+#define ID_AA64MMFR0_TGRAN64_NI                        0xf
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN     0x0
+#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX     0x7
+#define ID_AA64MMFR0_TGRAN16_NI                        0x0
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN     0x1
+#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX     0xf
+
 #define ID_AA64MMFR0_PARANGE_48                0x5
 #define ID_AA64MMFR0_PARANGE_52                0x6
 
@@ -961,16 +965,16 @@
 
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN4_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN4_SUPPORTED
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       0x7
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
 #elif defined(CONFIG_ARM64_16K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN16_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN16_SUPPORTED
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       0xF
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
 #elif defined(CONFIG_ARM64_64K_PAGES)
 #define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN64_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN64_SUPPORTED
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       0x7
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
+#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
 #endif
 
 #define MVFR2_FPMISC_SHIFT             4