drm/amd/display: Enable backlight support for pre-DCE11 ASICs

Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110
Adding constructors and destructors for each module.
Adding register list for DMCU in dce80 as some registers are missing
in dce80 from the basic list. DMCU is never used, so it would not have
any functional impact.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
index 1d4546f2313506a23449fccb137a834526bf0d23..c24c0e5ea44e7ecd0ea44b8732b94fa91577f8cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
@@ -46,6 +46,23 @@
        SR(SMU_INTERRUPT_CONTROL), \
        SR(DC_DMCU_SCRATCH)
 
+#define DMCU_DCE80_REG_LIST() \
+       SR(DMCU_CTRL), \
+       SR(DMCU_STATUS), \
+       SR(DMCU_RAM_ACCESS_CTRL), \
+       SR(DMCU_IRAM_WR_CTRL), \
+       SR(DMCU_IRAM_WR_DATA), \
+       SR(MASTER_COMM_DATA_REG1), \
+       SR(MASTER_COMM_DATA_REG2), \
+       SR(MASTER_COMM_DATA_REG3), \
+       SR(MASTER_COMM_CMD_REG), \
+       SR(MASTER_COMM_CNTL_REG), \
+       SR(DMCU_IRAM_RD_CTRL), \
+       SR(DMCU_IRAM_RD_DATA), \
+       SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
+       SR(SMU_INTERRUPT_CONTROL), \
+       SR(DC_DMCU_SCRATCH)
+
 #define DMCU_DCE110_COMMON_REG_LIST() \
        DMCU_COMMON_REG_LIST_DCE_BASE(), \
        SR(DCI_MEM_PWR_STATUS)
@@ -83,6 +100,24 @@
                        STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
        DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
 
+#define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
+       DMCU_SF(DMCU_CTRL, \
+                       DMCU_ENABLE, mask_sh), \
+       DMCU_SF(DMCU_STATUS, \
+                       UC_IN_STOP_MODE, mask_sh), \
+       DMCU_SF(DMCU_STATUS, \
+                       UC_IN_RESET, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_HOST_ACCESS_EN, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_WR_ADDR_AUTO_INC, mask_sh), \
+       DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
+                       IRAM_RD_ADDR_AUTO_INC, mask_sh), \
+       DMCU_SF(MASTER_COMM_CMD_REG, \
+                       MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
+       DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
+       DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
+
 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
        DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
        DMCU_SF(DCI_MEM_PWR_STATUS, \

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 3bdbed80f7f8a98d1511f4c97a07ba400c4df061..3092f76bdb75b2576a371c6a67a27c2c74d4967c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -51,6 +51,9 @@
 #include "dce/dce_10_0_d.h"
 #include "dce/dce_10_0_sh_mask.h"
 
+#include "dce/dce_dmcu.h"
+#include "dce/dce_abm.h"
+
 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
 #include "gmc/gmc_8_2_d.h"
 #include "gmc/gmc_8_2_sh_mask.h"
@@ -320,7 +323,29 @@ static const struct dce110_clk_src_mask cs_mask = {
                CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 };
 
+static const struct dce_dmcu_registers dmcu_regs = {
+               DMCU_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+               DMCU_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+               DMCU_MASK_SH_LIST_DCE110(_MASK)
+};
+
+static const struct dce_abm_registers abm_regs = {
+               ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+               ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
 
+static const struct dce_abm_mask abm_mask = {
+               ABM_MASK_SH_LIST_DCE110(_MASK)
+};
 
 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
 
@@ -622,6 +647,12 @@ static void destruct(struct dce110_resource_pool *pool)
        if (pool->base.display_clock != NULL)
                dce_disp_clk_destroy(&pool->base.display_clock);
 
+       if (pool->base.abm != NULL)
+                               dce_abm_destroy(&pool->base.abm);
+
+       if (pool->base.dmcu != NULL)
+                       dce_dmcu_destroy(&pool->base.dmcu);
+
        if (pool->base.irqs != NULL)
                dal_irq_service_destroy(&pool->base.irqs);
 }
@@ -829,6 +860,25 @@ static bool construct(
                goto res_create_fail;
        }
 
+       pool->base.dmcu = dce_dmcu_create(ctx,
+                       &dmcu_regs,
+                       &dmcu_shift,
+                       &dmcu_mask);
+       if (pool->base.dmcu == NULL) {
+               dm_error("DC: failed to create dmcu!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
+
+       pool->base.abm = dce_abm_create(ctx,
+                               &abm_regs,
+                               &abm_shift,
+                               &abm_mask);
+       if (pool->base.abm == NULL) {
+               dm_error("DC: failed to create abm!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
 
        /* get static clock information for PPLIB or firmware, save
         * max_clock_state

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index a36c14d3d9a86f586a468cad9517cb7bfa298b89..5d854a37a97896ee271ff9ebddcdffc6ff93310f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -53,6 +53,8 @@
 
 #include "reg_helper.h"
 
+#include "dce/dce_dmcu.h"
+#include "dce/dce_abm.h"
 /* TODO remove this include */
 
 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
@@ -364,6 +366,29 @@ static const struct resource_caps res_cap_83 = {
                .num_pll = 2,
 };
 
+static const struct dce_dmcu_registers dmcu_regs = {
+               DMCU_DCE80_REG_LIST()
+};
+
+static const struct dce_dmcu_shift dmcu_shift = {
+               DMCU_MASK_SH_LIST_DCE80(__SHIFT)
+};
+
+static const struct dce_dmcu_mask dmcu_mask = {
+               DMCU_MASK_SH_LIST_DCE80(_MASK)
+};
+static const struct dce_abm_registers abm_regs = {
+               ABM_DCE110_COMMON_REG_LIST()
+};
+
+static const struct dce_abm_shift abm_shift = {
+               ABM_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+               ABM_MASK_SH_LIST_DCE110(_MASK)
+};
+
 #define CTX  ctx
 #define REG(reg) mm ## reg
 
@@ -643,6 +668,12 @@ static void destruct(struct dce110_resource_pool *pool)
                }
        }
 
+       if (pool->base.abm != NULL)
+                       dce_abm_destroy(&pool->base.abm);
+
+       if (pool->base.dmcu != NULL)
+                       dce_dmcu_destroy(&pool->base.dmcu);
+
        if (pool->base.dp_clock_source != NULL)
                dce80_clock_source_destroy(&pool->base.dp_clock_source);
 
@@ -850,7 +881,25 @@ static bool dce80_construct(
                goto res_create_fail;
        }
 
+       pool->base.dmcu = dce_dmcu_create(ctx,
+                       &dmcu_regs,
+                       &dmcu_shift,
+                       &dmcu_mask);
+       if (pool->base.dmcu == NULL) {
+               dm_error("DC: failed to create dmcu!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
 
+       pool->base.abm = dce_abm_create(ctx,
+                       &abm_regs,
+                       &abm_shift,
+                       &abm_mask);
+       if (pool->base.abm == NULL) {
+               dm_error("DC: failed to create abm!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
                pool->base.display_clock->max_clks_state =
                                        static_clk_info.max_clocks_state;
@@ -1016,6 +1065,25 @@ static bool dce81_construct(
                goto res_create_fail;
        }
 
+       pool->base.dmcu = dce_dmcu_create(ctx,
+                       &dmcu_regs,
+                       &dmcu_shift,
+                       &dmcu_mask);
+       if (pool->base.dmcu == NULL) {
+               dm_error("DC: failed to create dmcu!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
+
+       pool->base.abm = dce_abm_create(ctx,
+                       &abm_regs,
+                       &abm_shift,
+                       &abm_mask);
+       if (pool->base.abm == NULL) {
+               dm_error("DC: failed to create abm!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
 
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
                pool->base.display_clock->max_clks_state =
@@ -1178,6 +1246,25 @@ static bool dce83_construct(
                goto res_create_fail;
        }
 
+       pool->base.dmcu = dce_dmcu_create(ctx,
+                       &dmcu_regs,
+                       &dmcu_shift,
+                       &dmcu_mask);
+       if (pool->base.dmcu == NULL) {
+               dm_error("DC: failed to create dmcu!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
+
+       pool->base.abm = dce_abm_create(ctx,
+                       &abm_regs,
+                       &abm_shift,
+                       &abm_mask);
+       if (pool->base.abm == NULL) {
+               dm_error("DC: failed to create abm!\n");
+               BREAK_TO_DEBUGGER();
+               goto res_create_fail;
+       }
 
        if (dm_pp_get_static_clocks(ctx, &static_clk_info))
                pool->base.display_clock->max_clks_state =