drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)

Add a workaround to fix BS-BS jitter issues on MST links, aligning
DPT/DPTP MTPs.

Bspec: 50050, 55424

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240129175533.904590-4-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index fc5455a55bd7a22cc4cc0d9196b390e3acab9399..641dd6113a2f830ade67fcd143df11723f7f3acd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1141,6 +1141,9 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
                        set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
                else if (crtc_state->fec_enable)
                        clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
+
+               if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
+                       set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
        }
 
        if (!clear && !set)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81eb36fa0837af30cc6f98075326aa4569031aca..7efcb31ccde5f2f40bd1deac45d3a932dc0a915e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4565,6 +4565,7 @@
 #define   GLK_CL0_PWR_DOWN             REG_BIT(10)
 
 #define CHICKEN_MISC_3         _MMIO(0x42088)
+#define   DP_MST_DPT_DPTP_ALIGN_WA(trans)      REG_BIT(9 + (trans) - TRANSCODER_A)
 #define   DP_MST_SHORT_HBLANK_WA(trans)                REG_BIT(5 + (trans) - TRANSCODER_A)
 #define   DP_MST_FEC_BS_JITTER_WA(trans)       REG_BIT(0 + (trans) - TRANSCODER_A)