drm/amdgpu: Reconfigure ULV for gfx9 server SKUs

SDMA ULV can benefit low-power modes, but can sometimes cause
latency increases in small SDMA transfers. Server SKUs have a
different trade-off space in this domain, so this configures
the server SKUs' ULV hysteresis times differently than consumer
SKUs'.

Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 234976c585cb4c29ee93d8a60b52cef542b37856..aaa90a181cad929ad8492c4ce8f9b48d161284ce 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -505,6 +505,36 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
        }
 }
 
+static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
+{
+       int i;
+
+       /*
+        * The only chips with SDMAv4 and ULV are VG10 and VG20.
+        * Server SKUs take a different hysteresis setting from other SKUs.
+        */
+       switch (adev->asic_type) {
+       case CHIP_VEGA10:
+               if (adev->pdev->device == 0x6860)
+                       break;
+               return;
+       case CHIP_VEGA20:
+               if (adev->pdev->device == 0x66a1)
+                       break;
+               return;
+       default:
+               return;
+       }
+
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               uint32_t temp;
+
+               temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
+               temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
+               WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
+       }
+}
+
 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 {
        int err = 0;
@@ -1813,6 +1843,8 @@ static int sdma_v4_0_late_init(void *handle)
                .cb = sdma_v4_0_process_ras_data_cb,
        };
 
+       sdma_v4_0_setup_ulv(adev);
+
        if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
                adev->sdma.funcs->reset_ras_error_count(adev);