"[GetNumOfDpmLevel] failed to get dpm levels!",
return ret);
- vega20_read_arg_from_smc(hwmgr, num_of_levels);
+ *num_of_levels = smum_get_argument(hwmgr);
PP_ASSERT_WITH_CODE(*num_of_levels > 0,
"[GetNumOfDpmLevel] number of clk levels is invalid!",
return -EINVAL);
"[GetDpmFreqByIndex] failed to get dpm freq by index!",
return ret);
- vega20_read_arg_from_smc(hwmgr, clk);
+ *clk = smum_get_argument(hwmgr);
PP_ASSERT_WITH_CODE(*clk,
"[GetDpmFreqByIndex] clk value is invalid!",
return -EINVAL);
"[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
return ret);
- vega20_read_arg_from_smc(hwmgr, voltage);
+ *voltage = smum_get_argument(hwmgr);
*voltage = *voltage / VOLTAGE_SCALE;
return 0;
(clock_select << 16))) == 0,
"[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
return ret);
- vega20_read_arg_from_smc(hwmgr, clock);
+ *clock = smum_get_argument(hwmgr);
/* if DC limit is zero, return AC limit */
if (*clock == 0) {
(clock_select << 16))) == 0,
"[GetMaxSustainableClock] failed to get max AC clock from SMC!",
return ret);
- vega20_read_arg_from_smc(hwmgr, clock);
+ *clock = smum_get_argument(hwmgr);
}
return 0;
PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
"[GetClockRanges] Failed to get max clock from SMC!",
return ret);
- vega20_read_arg_from_smc(hwmgr, clock);
+ *clock = smum_get_argument(hwmgr);
} else {
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GetMinDpmFreq,
(clock_select << 16))) == 0,
"[GetClockRanges] Failed to get min clock from SMC!",
return ret);
- vega20_read_arg_from_smc(hwmgr, clock);
+ *clock = smum_get_argument(hwmgr);
}
return 0;
PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16))) == 0,
"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
return ret);
- vega20_read_arg_from_smc(hwmgr, &gfx_clk);
+ gfx_clk = smum_get_argument(hwmgr);
*gfx_freq = gfx_clk * 100;
PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16))) == 0,
"[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
return ret);
- vega20_read_arg_from_smc(hwmgr, &mem_clk);
+ mem_clk = smum_get_argument(hwmgr);
*mclk_freq = mem_clk * 100;
return (ret == PPSMC_Result_OK) ? 0 : -EIO;
}
-/*
- * Retrieve an argument from SMC.
- * @param hwmgr the address of the powerplay hardware manager.
- * @param arg pointer to store the argument from SMC.
- * @return Always return 0.
- */
-int vega20_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
+static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
{
struct amdgpu_device *adev = hwmgr->adev;
- *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
-
- return 0;
+ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
}
/*
PPSMC_MSG_GetEnabledSmuFeaturesLow)) == 0,
"[GetEnabledSMCFeatures] Attemp to get SMU features Low failed!",
return ret);
- PP_ASSERT_WITH_CODE((ret = vega20_read_arg_from_smc(hwmgr,
- &smc_features_low)) == 0,
- "[GetEnabledSMCFeatures] Attemp to read SMU features Low argument failed!",
- return ret);
+ smc_features_low = vega20_get_argument(hwmgr);
PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetEnabledSmuFeaturesHigh)) == 0,
"[GetEnabledSMCFeatures] Attemp to get SMU features High failed!",
return ret);
- PP_ASSERT_WITH_CODE((ret = vega20_read_arg_from_smc(hwmgr,
- &smc_features_high)) == 0,
- "[GetEnabledSMCFeatures] Attemp to read SMU features High argument failed!",
- return ret);
+ smc_features_high = vega20_get_argument(hwmgr);
*features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
(((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
.is_dpm_running = vega20_is_dpm_running,
+ .get_argument = vega20_get_argument,
};