drm/i915: pass dev_priv explicitly to DSPTILEOFF

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPTILEOFF register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/4736b2d65ca3be3e9eb5a835ddac801ba99e1e6b.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 7adaf8cbd9452776551f6c331a97676aa68b3bc4..36225c2aa1c88cca957a64e178e1cba300066518 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -487,7 +487,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
        } else if (DISPLAY_VER(dev_priv) >= 4) {
                intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
                                  linear_offset);
-               intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
+               intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane),
                                  DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
        }
 
@@ -1038,7 +1038,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
        } else if (DISPLAY_VER(dev_priv) >= 4) {
                if (plane_config->tiling)
                        offset = intel_de_read(dev_priv,
-                                              DSPTILEOFF(i9xx_plane));
+                                              DSPTILEOFF(dev_priv, i9xx_plane));
                else
                        offset = intel_de_read(dev_priv,
                                               DSPLINOFF(dev_priv, i9xx_plane));

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 2771f2a7645b228c2a4a9a79abc4206b0aa952ff..baa3d348c77eb9a760af376ee2c5f1339ca88edc 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -71,7 +71,7 @@
 #define   DISP_ADDR_MASK               REG_GENMASK(31, 12)
 
 #define _DSPATILEOFF                           0x701A4 /* i965+ */
-#define DSPTILEOFF(plane)                      _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
+#define DSPTILEOFF(dev_priv, plane)            _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
 #define   DISP_OFFSET_Y_MASK           REG_GENMASK(31, 16)
 #define   DISP_OFFSET_Y(y)             REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
 #define   DISP_OFFSET_X_MASK           REG_GENMASK(15, 0)

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6c3a0f160bea7e4f8b0e6453e9fba177074bb6f6..0afde865a7deb3e911cb30d9f9183781fdf87330 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -274,7 +274,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
                        _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
        plane->height += 1;     /* raw height is one minus the real value */
 
-       val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
+       val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
        plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
                _PRI_PLANE_X_OFF_SHIFT;
        plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>