drm/radeon/kms: add module option for pcie gen2
authorAlex Deucher <alexdeucher@gmail.com>
Thu, 13 Jan 2011 01:05:11 +0000 (20:05 -0500)
committerDave Airlie <airlied@redhat.com>
Mon, 17 Jan 2011 02:21:34 +0000 (12:21 +1000)
Switching to pcie gen2 causes problems on some
boards.  Add a module option to turn it on/off.

There are gen2 compatability issues with some
motherboards it seems.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=33027

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/radeon/rv770.c

index 7fe8ebdcdc0ec59d1128520f5610633bf8379814..e201a88caf590c592ba8b826aede3dc45b17cd95 100644 (file)
@@ -3158,6 +3158,9 @@ static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 {
        u32 link_width_cntl, speed_cntl;
 
+       if (radeon_pcie_gen2 == 0)
+               return;
+
        if (rdev->flags & RADEON_IS_IGP)
                return;
 
index 6b50716267c0911650f2d6103c7a17b5f9d0bd87..9fe86253cfcd756a7a36d6f1de7e917d35ad0545 100644 (file)
@@ -3658,6 +3658,9 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
        u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
        u16 link_cntl2;
 
+       if (radeon_pcie_gen2 == 0)
+               return;
+
        if (rdev->flags & RADEON_IS_IGP)
                return;
 
index e9486630a46721504241a4ec593597240d0dc95b..71d2a554bbe69f8dce44d05e0bbde059775a4be6 100644 (file)
@@ -92,6 +92,7 @@ extern int radeon_tv;
 extern int radeon_audio;
 extern int radeon_disp_priority;
 extern int radeon_hw_i2c;
+extern int radeon_pcie_gen2;
 
 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
index be5cb4f28c294b0713d915db5ae60c669e8e3aff..d5680a0c87af4a557d18e12f30626a98ed6fae59 100644 (file)
@@ -104,6 +104,7 @@ int radeon_tv = 1;
 int radeon_audio = 1;
 int radeon_disp_priority = 0;
 int radeon_hw_i2c = 0;
+int radeon_pcie_gen2 = 0;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -147,6 +148,9 @@ module_param_named(disp_priority, radeon_disp_priority, int, 0444);
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
 
+MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)");
+module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
+
 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
index 3a264aa3a79afbc3de4d3d07b78f1d49f44c07d9..bd9ee90421e409ed6c440f641c9bb4a3ab8287cc 100644 (file)
@@ -1372,6 +1372,9 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
        u32 link_width_cntl, lanes, speed_cntl, tmp;
        u16 link_cntl2;
 
+       if (radeon_pcie_gen2 == 0)
+               return;
+
        if (rdev->flags & RADEON_IS_IGP)
                return;