Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late fixes and dependencies from Kevin Hilman:
 "This is a collection of a few late fixes and other misc stuff that had
  dependencies on things being merged from other trees.

  Other than the fixes, the primary feature being added is the
  conversion of some OMAP drivers to the new generic wakeirq interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: multi_v7_defconfig: Enable BRCMNAND driver
  ARM: BCM: Do not select CONFIG_MTD_NAND_BRCMNAND
  ARM: at91/dt: update udc compatible strings
  ARM: at91/dt: trivial: fix USB udc compatible string
  arm64: dts: Add APM X-Gene standby GPIO controller DTS entries
  soc: qcom: spm: Fix idle on THUMB2 kernels
  ARM: dove: fix legacy dove IRQ numbers
  ARM: mvebu: fix suspend to RAM on big-endian configurations
  ARM: mvebu: adjust Armada XP DT spi muxing after pinctrl function rename
  serial: 8250_omap: Move wake-up interrupt to generic wakeirq
  serial: omap: Switch wake-up interrupt to generic wakeirq
  mmc: omap_hsmmc: Change wake-up interrupt to use generic wakeirq

diff --combined arch/arm/boot/dts/armada-xp.dtsi
index 0854d4493da7a8518c241dabe06e91ce22eb5fe9,58eaef46efd5a3460b09f644edb27d01914eecc8..3de9b761cc1ab0fe7a8d3f0ea9caa7ca72e2a989
--- 1/arch/arm/boot/dts/armada-xp.dtsi
--- 2/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@@ -185,7 -185,7 +185,7 @@@
                        };
  
                        eth2: ethernet@30000 {
 -                              compatible = "marvell,armada-370-neta";
 +                              compatible = "marvell,armada-xp-neta";
                                reg = <0x30000 0x4000>;
                                interrupts = <12>;
                                clocks = <&gateclk 2>;
@@@ -228,14 -228,6 +228,14 @@@
                                };
                        };
  
 +                      ethernet@70000 {
 +                              compatible = "marvell,armada-xp-neta";
 +                      };
 +
 +                      ethernet@74000 {
 +                              compatible = "marvell,armada-xp-neta";
 +                      };
 +
                        xor@f0900 {
                                compatible = "marvell,orion-xor";
                                reg = <0xF0900 0x100
@@@ -305,7 -297,7 +305,7 @@@
        spi0_pins: spi0-pins {
                marvell,pins = "mpp36", "mpp37",
                               "mpp38", "mpp39";
-               marvell,function = "spi";
+               marvell,function = "spi0";
        };
  
        uart2_pins: uart2-pins {

diff --combined arch/arm64/boot/dts/apm/apm-storm.dtsi
index 0bb287ca0a98e8dcaac6ebd6497d762005b27013,6bbab95307aee5222e579b6382771f89e99e9b60..0689c3fb56e3d84fe3ed7790f4a6b25835c86555
--- 1/arch/arm64/boot/dts/apm/apm-storm.dtsi
--- 2/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@@ -374,111 -374,6 +374,111 @@@
                        };
                };
  
 +              msi: msi@79000000 {
 +                      compatible = "apm,xgene1-msi";
 +                      msi-controller;
 +                      reg = <0x00 0x79000000 0x0 0x900000>;
 +                      interrupts = <  0x0 0x10 0x4
 +                                      0x0 0x11 0x4
 +                                      0x0 0x12 0x4
 +                                      0x0 0x13 0x4
 +                                      0x0 0x14 0x4
 +                                      0x0 0x15 0x4
 +                                      0x0 0x16 0x4
 +                                      0x0 0x17 0x4
 +                                      0x0 0x18 0x4
 +                                      0x0 0x19 0x4
 +                                      0x0 0x1a 0x4
 +                                      0x0 0x1b 0x4
 +                                      0x0 0x1c 0x4
 +                                      0x0 0x1d 0x4
 +                                      0x0 0x1e 0x4
 +                                      0x0 0x1f 0x4>;
 +              };
 +
 +              csw: csw@7e200000 {
 +                      compatible = "apm,xgene-csw", "syscon";
 +                      reg = <0x0 0x7e200000 0x0 0x1000>;
 +              };
 +
 +              mcba: mcba@7e700000 {
 +                      compatible = "apm,xgene-mcb", "syscon";
 +                      reg = <0x0 0x7e700000 0x0 0x1000>;
 +              };
 +
 +              mcbb: mcbb@7e720000 {
 +                      compatible = "apm,xgene-mcb", "syscon";
 +                      reg = <0x0 0x7e720000 0x0 0x1000>;
 +              };
 +
 +              efuse: efuse@1054a000 {
 +                      compatible = "apm,xgene-efuse", "syscon";
 +                      reg = <0x0 0x1054a000 0x0 0x20>;
 +              };
 +
 +              edac@78800000 {
 +                      compatible = "apm,xgene-edac";
 +                      #address-cells = <2>;
 +                      #size-cells = <2>;
 +                      ranges;
 +                      regmap-csw = <&csw>;
 +                      regmap-mcba = <&mcba>;
 +                      regmap-mcbb = <&mcbb>;
 +                      regmap-efuse = <&efuse>;
 +                      reg = <0x0 0x78800000 0x0 0x100>;
 +                      interrupts = <0x0 0x20 0x4>,
 +                                   <0x0 0x21 0x4>,
 +                                   <0x0 0x27 0x4>;
 +
 +                      edacmc@7e800000 {
 +                              compatible = "apm,xgene-edac-mc";
 +                              reg = <0x0 0x7e800000 0x0 0x1000>;
 +                              memory-controller = <0>;
 +                      };
 +
 +                      edacmc@7e840000 {
 +                              compatible = "apm,xgene-edac-mc";
 +                              reg = <0x0 0x7e840000 0x0 0x1000>;
 +                              memory-controller = <1>;
 +                      };
 +
 +                      edacmc@7e880000 {
 +                              compatible = "apm,xgene-edac-mc";
 +                              reg = <0x0 0x7e880000 0x0 0x1000>;
 +                              memory-controller = <2>;
 +                      };
 +
 +                      edacmc@7e8c0000 {
 +                              compatible = "apm,xgene-edac-mc";
 +                              reg = <0x0 0x7e8c0000 0x0 0x1000>;
 +                              memory-controller = <3>;
 +                      };
 +
 +                      edacpmd@7c000000 {
 +                              compatible = "apm,xgene-edac-pmd";
 +                              reg = <0x0 0x7c000000 0x0 0x200000>;
 +                              pmd-controller = <0>;
 +                      };
 +
 +                      edacpmd@7c200000 {
 +                              compatible = "apm,xgene-edac-pmd";
 +                              reg = <0x0 0x7c200000 0x0 0x200000>;
 +                              pmd-controller = <1>;
 +                      };
 +
 +                      edacpmd@7c400000 {
 +                              compatible = "apm,xgene-edac-pmd";
 +                              reg = <0x0 0x7c400000 0x0 0x200000>;
 +                              pmd-controller = <2>;
 +                      };
 +
 +                      edacpmd@7c600000 {
 +                              compatible = "apm,xgene-edac-pmd";
 +                              reg = <0x0 0x7c600000 0x0 0x200000>;
 +                              pmd-controller = <3>;
 +                      };
 +              };
 +
                pcie0: pcie@1f2b0000 {
                        status = "disabled";
                        device_type = "pci";
@@@ -500,7 -395,6 +500,7 @@@
                                         0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
                        dma-coherent;
                        clocks = <&pcie0clk 0>;
 +                      msi-parent = <&msi>;
                };
  
                pcie1: pcie@1f2c0000 {
@@@ -524,7 -418,6 +524,7 @@@
                                         0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
                        dma-coherent;
                        clocks = <&pcie1clk 0>;
 +                      msi-parent = <&msi>;
                };
  
                pcie2: pcie@1f2d0000 {
@@@ -548,7 -441,6 +548,7 @@@
                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
                        dma-coherent;
                        clocks = <&pcie2clk 0>;
 +                      msi-parent = <&msi>;
                };
  
                pcie3: pcie@1f500000 {
@@@ -572,7 -464,6 +572,7 @@@
                                         0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
                        dma-coherent;
                        clocks = <&pcie3clk 0>;
 +                      msi-parent = <&msi>;
                };
  
                pcie4: pcie@1f510000 {
@@@ -596,7 -487,6 +596,7 @@@
                                         0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
                        dma-coherent;
                        clocks = <&pcie4clk 0>;
 +                      msi-parent = <&msi>;
                };
  
                serial0: serial@1c020000 {
@@@ -717,6 -607,19 +717,19 @@@
                        phy-names = "sata-phy";
                };
  
+               sbgpio: sbgpio@17001000{
+                       compatible = "apm,xgene-gpio-sb";
+                       reg = <0x0 0x17001000 0x0 0x400>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       interrupts =    <0x0 0x28 0x1>,
+                                       <0x0 0x29 0x1>,
+                                       <0x0 0x2a 0x1>,
+                                       <0x0 0x2b 0x1>,
+                                       <0x0 0x2c 0x1>,
+                                       <0x0 0x2d 0x1>;
+               };
+ 
                rtc: rtc@10510000 {
                        compatible = "apm,xgene-rtc";
                        reg = <0x0 0x10510000 0x0 0x400>;