extern int amdgpu_mes_log_enable;
extern int amdgpu_mes_kiq;
extern int amdgpu_uni_mes;
+extern int amdgpu_jpeg_test;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
/* jpeg */
struct amdgpu_jpeg jpeg;
+ bool enable_jpeg_test;
/* vpe */
struct amdgpu_vpe vpe;
case IP_VERSION(5, 0, 0):
amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
+ if (amdgpu_jpeg_test)
+ adev->enable_jpeg_test = true;
break;
default:
dev_err(adev->dev,
int amdgpu_tmz = -1; /* auto */
uint amdgpu_freesync_vid_mode;
int amdgpu_reset_method = -1; /* auto */
+int amdgpu_jpeg_test;
int amdgpu_num_kcq = -1;
int amdgpu_smartshift_bias;
int amdgpu_use_xgmi_p2p = 1;
MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
module_param_named(reset_method, amdgpu_reset_method, int, 0644);
+MODULE_PARM_DESC(jpeg_test, "jpeg test(0 = disable (default), 1 = enable)");
+module_param_named(jpeg_test, amdgpu_jpeg_test, int, 0444);
+
/**
* DOC: bad_page_threshold (int) Bad page threshold is specifies the
* threshold value of faulty pages detected by RAS ECC, which may