perf vendor events riscv: Rename U74 to Bullet

This set of PMU event descriptions applies not only to the SiFive U74
core configuration, but also to other SiFive cores that implement the
Bullet microarchitecture (such as U64, P270, and X280). Rename the
directory to be more generic.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-2-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>

diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 3d3a809a5446e8e811dcd6cc243c33c58811e0b1..521f416b000609d009d197bea38a3a408d362b89 100644 (file)
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -14,7 +14,7 @@
 #
 #
 #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
-0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core
 0x5b7-0x0-0x0,v1,thead/c900-legacy,core
 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json
new file mode 100644 (file)
index 0000000..7149cae
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/firmware.json
@@ -0,0 +1,68 @@
+[
+  {
+    "ArchStdEvent": "FW_MISALIGNED_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_MISALIGNED_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_LOAD"
+  },
+  {
+    "ArchStdEvent": "FW_ACCESS_STORE"
+  },
+  {
+    "ArchStdEvent": "FW_ILLEGAL_INSN"
+  },
+  {
+    "ArchStdEvent": "FW_SET_TIMER"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_IPI_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+  },
+  {
+    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+  }
+]

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
new file mode 100644 (file)
index 0000000..5eab718
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
@@ -0,0 +1,92 @@
+[
+  {
+    "EventName": "EXCEPTION_TAKEN",
+    "EventCode": "0x0000100",
+    "BriefDescription": "Exception taken"
+  },
+  {
+    "EventName": "INTEGER_LOAD_RETIRED",
+    "EventCode": "0x0000200",
+    "BriefDescription": "Integer load instruction retired"
+  },
+  {
+    "EventName": "INTEGER_STORE_RETIRED",
+    "EventCode": "0x0000400",
+    "BriefDescription": "Integer store instruction retired"
+  },
+  {
+    "EventName": "ATOMIC_MEMORY_RETIRED",
+    "EventCode": "0x0000800",
+    "BriefDescription": "Atomic memory operation retired"
+  },
+  {
+    "EventName": "SYSTEM_INSTRUCTION_RETIRED",
+    "EventCode": "0x0001000",
+    "BriefDescription": "System instruction retired"
+  },
+  {
+    "EventName": "INTEGER_ARITHMETIC_RETIRED",
+    "EventCode": "0x0002000",
+    "BriefDescription": "Integer arithmetic instruction retired"
+  },
+  {
+    "EventName": "CONDITIONAL_BRANCH_RETIRED",
+    "EventCode": "0x0004000",
+    "BriefDescription": "Conditional branch retired"
+  },
+  {
+    "EventName": "JAL_INSTRUCTION_RETIRED",
+    "EventCode": "0x0008000",
+    "BriefDescription": "JAL instruction retired"
+  },
+  {
+    "EventName": "JALR_INSTRUCTION_RETIRED",
+    "EventCode": "0x0010000",
+    "BriefDescription": "JALR instruction retired"
+  },
+  {
+    "EventName": "INTEGER_MULTIPLICATION_RETIRED",
+    "EventCode": "0x0020000",
+    "BriefDescription": "Integer multiplication instruction retired"
+  },
+  {
+    "EventName": "INTEGER_DIVISION_RETIRED",
+    "EventCode": "0x0040000",
+    "BriefDescription": "Integer division instruction retired"
+  },
+  {
+    "EventName": "FP_LOAD_RETIRED",
+    "EventCode": "0x0080000",
+    "BriefDescription": "Floating-point load instruction retired"
+  },
+  {
+    "EventName": "FP_STORE_RETIRED",
+    "EventCode": "0x0100000",
+    "BriefDescription": "Floating-point store instruction retired"
+  },
+  {
+    "EventName": "FP_ADDITION_RETIRED",
+    "EventCode": "0x0200000",
+    "BriefDescription": "Floating-point addition retired"
+  },
+  {
+    "EventName": "FP_MULTIPLICATION_RETIRED",
+    "EventCode": "0x0400000",
+    "BriefDescription": "Floating-point multiplication retired"
+  },
+  {
+    "EventName": "FP_FUSEDMADD_RETIRED",
+    "EventCode": "0x0800000",
+    "BriefDescription": "Floating-point fused multiply-add retired"
+  },
+  {
+    "EventName": "FP_DIV_SQRT_RETIRED",
+    "EventCode": "0x1000000",
+    "BriefDescription": "Floating-point division or square-root retired"
+  },
+  {
+    "EventName": "OTHER_FP_RETIRED",
+    "EventCode": "0x2000000",
+    "BriefDescription": "Other floating-point instruction retired"
+  }
+]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
new file mode 100644 (file)
index 0000000..be1a463
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
@@ -0,0 +1,32 @@
+[
+  {
+    "EventName": "ICACHE_RETIRED",
+    "EventCode": "0x0000102",
+    "BriefDescription": "Instruction cache miss"
+  },
+  {
+    "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+    "EventCode": "0x0000202",
+    "BriefDescription": "Data cache miss or memory-mapped I/O access"
+  },
+  {
+    "EventName": "DCACHE_WRITEBACK",
+    "EventCode": "0x0000402",
+    "BriefDescription": "Data cache write-back"
+  },
+  {
+    "EventName": "INST_TLB_MISS",
+    "EventCode": "0x0000802",
+    "BriefDescription": "Instruction TLB miss"
+  },
+  {
+    "EventName": "DATA_TLB_MISS",
+    "EventCode": "0x0001002",
+    "BriefDescription": "Data TLB miss"
+  },
+  {
+    "EventName": "UTLB_MISS",
+    "EventCode": "0x0002002",
+    "BriefDescription": "UTLB miss"
+  }
+]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
new file mode 100644 (file)
index 0000000..50ffa55
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
@@ -0,0 +1,57 @@
+[
+  {
+    "EventName": "ADDRESSGEN_INTERLOCK",
+    "EventCode": "0x0000101",
+    "BriefDescription": "Address-generation interlock"
+  },
+  {
+    "EventName": "LONGLAT_INTERLOCK",
+    "EventCode": "0x0000201",
+    "BriefDescription": "Long-latency interlock"
+  },
+  {
+    "EventName": "CSR_READ_INTERLOCK",
+    "EventCode": "0x0000401",
+    "BriefDescription": "CSR read interlock"
+  },
+  {
+    "EventName": "ICACHE_ITIM_BUSY",
+    "EventCode": "0x0000801",
+    "BriefDescription": "Instruction cache/ITIM busy"
+  },
+  {
+    "EventName": "DCACHE_DTIM_BUSY",
+    "EventCode": "0x0001001",
+    "BriefDescription": "Data cache/DTIM busy"
+  },
+  {
+    "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+    "EventCode": "0x0002001",
+    "BriefDescription": "Branch direction misprediction"
+  },
+  {
+    "EventName": "BRANCH_TARGET_MISPREDICTION",
+    "EventCode": "0x0004001",
+    "BriefDescription": "Branch/jump target misprediction"
+  },
+  {
+    "EventName": "PIPE_FLUSH_CSR_WRITE",
+    "EventCode": "0x0008001",
+    "BriefDescription": "Pipeline flush from CSR write"
+  },
+  {
+    "EventName": "PIPE_FLUSH_OTHER_EVENT",
+    "EventCode": "0x0010001",
+    "BriefDescription": "Pipeline flush from other event"
+  },
+  {
+    "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+    "EventCode": "0x0020001",
+    "BriefDescription": "Integer multiplication interlock"
+  },
+  {
+    "EventName": "FP_INTERLOCK",
+    "EventCode": "0x0040001",
+    "BriefDescription": "Floating-point interlock"
+  }
+]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
deleted file mode 100644 (file)
index 7149cae..0000000
--- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
+++ /dev/null
@@ -1,68 +0,0 @@
-[
-  {
-    "ArchStdEvent": "FW_MISALIGNED_LOAD"
-  },
-  {
-    "ArchStdEvent": "FW_MISALIGNED_STORE"
-  },
-  {
-    "ArchStdEvent": "FW_ACCESS_LOAD"
-  },
-  {
-    "ArchStdEvent": "FW_ACCESS_STORE"
-  },
-  {
-    "ArchStdEvent": "FW_ILLEGAL_INSN"
-  },
-  {
-    "ArchStdEvent": "FW_SET_TIMER"
-  },
-  {
-    "ArchStdEvent": "FW_IPI_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_IPI_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_FENCE_I_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_FENCE_I_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_SFENCE_VMA_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
-  },
-  {
-    "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
-  }
-]

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
deleted file mode 100644 (file)
index 5eab718..0000000
--- a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
+++ /dev/null
@@ -1,92 +0,0 @@
-[
-  {
-    "EventName": "EXCEPTION_TAKEN",
-    "EventCode": "0x0000100",
-    "BriefDescription": "Exception taken"
-  },
-  {
-    "EventName": "INTEGER_LOAD_RETIRED",
-    "EventCode": "0x0000200",
-    "BriefDescription": "Integer load instruction retired"
-  },
-  {
-    "EventName": "INTEGER_STORE_RETIRED",
-    "EventCode": "0x0000400",
-    "BriefDescription": "Integer store instruction retired"
-  },
-  {
-    "EventName": "ATOMIC_MEMORY_RETIRED",
-    "EventCode": "0x0000800",
-    "BriefDescription": "Atomic memory operation retired"
-  },
-  {
-    "EventName": "SYSTEM_INSTRUCTION_RETIRED",
-    "EventCode": "0x0001000",
-    "BriefDescription": "System instruction retired"
-  },
-  {
-    "EventName": "INTEGER_ARITHMETIC_RETIRED",
-    "EventCode": "0x0002000",
-    "BriefDescription": "Integer arithmetic instruction retired"
-  },
-  {
-    "EventName": "CONDITIONAL_BRANCH_RETIRED",
-    "EventCode": "0x0004000",
-    "BriefDescription": "Conditional branch retired"
-  },
-  {
-    "EventName": "JAL_INSTRUCTION_RETIRED",
-    "EventCode": "0x0008000",
-    "BriefDescription": "JAL instruction retired"
-  },
-  {
-    "EventName": "JALR_INSTRUCTION_RETIRED",
-    "EventCode": "0x0010000",
-    "BriefDescription": "JALR instruction retired"
-  },
-  {
-    "EventName": "INTEGER_MULTIPLICATION_RETIRED",
-    "EventCode": "0x0020000",
-    "BriefDescription": "Integer multiplication instruction retired"
-  },
-  {
-    "EventName": "INTEGER_DIVISION_RETIRED",
-    "EventCode": "0x0040000",
-    "BriefDescription": "Integer division instruction retired"
-  },
-  {
-    "EventName": "FP_LOAD_RETIRED",
-    "EventCode": "0x0080000",
-    "BriefDescription": "Floating-point load instruction retired"
-  },
-  {
-    "EventName": "FP_STORE_RETIRED",
-    "EventCode": "0x0100000",
-    "BriefDescription": "Floating-point store instruction retired"
-  },
-  {
-    "EventName": "FP_ADDITION_RETIRED",
-    "EventCode": "0x0200000",
-    "BriefDescription": "Floating-point addition retired"
-  },
-  {
-    "EventName": "FP_MULTIPLICATION_RETIRED",
-    "EventCode": "0x0400000",
-    "BriefDescription": "Floating-point multiplication retired"
-  },
-  {
-    "EventName": "FP_FUSEDMADD_RETIRED",
-    "EventCode": "0x0800000",
-    "BriefDescription": "Floating-point fused multiply-add retired"
-  },
-  {
-    "EventName": "FP_DIV_SQRT_RETIRED",
-    "EventCode": "0x1000000",
-    "BriefDescription": "Floating-point division or square-root retired"
-  },
-  {
-    "EventName": "OTHER_FP_RETIRED",
-    "EventCode": "0x2000000",
-    "BriefDescription": "Other floating-point instruction retired"
-  }
-]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
deleted file mode 100644 (file)
index be1a463..0000000
--- a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
+++ /dev/null
@@ -1,32 +0,0 @@
-[
-  {
-    "EventName": "ICACHE_RETIRED",
-    "EventCode": "0x0000102",
-    "BriefDescription": "Instruction cache miss"
-  },
-  {
-    "EventName": "DCACHE_MISS_MMIO_ACCESSES",
-    "EventCode": "0x0000202",
-    "BriefDescription": "Data cache miss or memory-mapped I/O access"
-  },
-  {
-    "EventName": "DCACHE_WRITEBACK",
-    "EventCode": "0x0000402",
-    "BriefDescription": "Data cache write-back"
-  },
-  {
-    "EventName": "INST_TLB_MISS",
-    "EventCode": "0x0000802",
-    "BriefDescription": "Instruction TLB miss"
-  },
-  {
-    "EventName": "DATA_TLB_MISS",
-    "EventCode": "0x0001002",
-    "BriefDescription": "Data TLB miss"
-  },
-  {
-    "EventName": "UTLB_MISS",
-    "EventCode": "0x0002002",
-    "BriefDescription": "UTLB miss"
-  }
-]
\ No newline at end of file

diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
deleted file mode 100644 (file)
index 50ffa55..0000000
--- a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
+++ /dev/null
@@ -1,57 +0,0 @@
-[
-  {
-    "EventName": "ADDRESSGEN_INTERLOCK",
-    "EventCode": "0x0000101",
-    "BriefDescription": "Address-generation interlock"
-  },
-  {
-    "EventName": "LONGLAT_INTERLOCK",
-    "EventCode": "0x0000201",
-    "BriefDescription": "Long-latency interlock"
-  },
-  {
-    "EventName": "CSR_READ_INTERLOCK",
-    "EventCode": "0x0000401",
-    "BriefDescription": "CSR read interlock"
-  },
-  {
-    "EventName": "ICACHE_ITIM_BUSY",
-    "EventCode": "0x0000801",
-    "BriefDescription": "Instruction cache/ITIM busy"
-  },
-  {
-    "EventName": "DCACHE_DTIM_BUSY",
-    "EventCode": "0x0001001",
-    "BriefDescription": "Data cache/DTIM busy"
-  },
-  {
-    "EventName": "BRANCH_DIRECTION_MISPREDICTION",
-    "EventCode": "0x0002001",
-    "BriefDescription": "Branch direction misprediction"
-  },
-  {
-    "EventName": "BRANCH_TARGET_MISPREDICTION",
-    "EventCode": "0x0004001",
-    "BriefDescription": "Branch/jump target misprediction"
-  },
-  {
-    "EventName": "PIPE_FLUSH_CSR_WRITE",
-    "EventCode": "0x0008001",
-    "BriefDescription": "Pipeline flush from CSR write"
-  },
-  {
-    "EventName": "PIPE_FLUSH_OTHER_EVENT",
-    "EventCode": "0x0010001",
-    "BriefDescription": "Pipeline flush from other event"
-  },
-  {
-    "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
-    "EventCode": "0x0020001",
-    "BriefDescription": "Integer multiplication interlock"
-  },
-  {
-    "EventName": "FP_INTERLOCK",
-    "EventCode": "0x0040001",
-    "BriefDescription": "Floating-point interlock"
-  }
-]
\ No newline at end of file