arm64: dts: qcom: x1e80100: align mem timer size cells with bindings

The ARMv7 memory mapped architected timer bindings expect MMIO sizes up
to 32-bit.  Keep 64-bit addressing but change the size of memory mapping
to 32-bit (size-cells=1) and adjust the ranges to match this.

This fixes dtbs_check warnings like:

  x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231218150656.72892-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index da691e2f32099876be13b5e3fca9405c5e4da9b1..6f75fc342ceb38168f5ae33bfc490a1003eed755 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3418,12 +3418,12 @@
                        reg = <0 0x17800000 0 0x1000>;
 
                        #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       #size-cells = <1>;
+                       ranges = <0 0 0 0 0x20000000>;
 
                        frame@17801000 {
-                               reg = <0 0x17801000 0 0x1000>,
-                                     <0 0x17802000 0 0x1000>;
+                               reg = <0 0x17801000 0x1000>,
+                                     <0 0x17802000 0x1000>;
 
                                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                                             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -3432,7 +3432,7 @@
                        };
 
                        frame@17803000 {
-                               reg = <0 0x17803000 0 0x1000>;
+                               reg = <0 0x17803000 0x1000>;
 
                                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3442,7 +3442,7 @@
                        };
 
                        frame@17805000 {
-                               reg = <0 0x17805000 0 0x1000>;
+                               reg = <0 0x17805000 0x1000>;
 
                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3452,7 +3452,7 @@
                        };
 
                        frame@17807000 {
-                               reg = <0 0x17807000 0 0x1000>;
+                               reg = <0 0x17807000 0x1000>;
 
                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3462,7 +3462,7 @@
                        };
 
                        frame@17809000 {
-                               reg = <0 0x17809000 0 0x1000>;
+                               reg = <0 0x17809000 0x1000>;
 
                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3472,7 +3472,7 @@
                        };
 
                        frame@1780b000 {
-                               reg = <0 0x1780b000 0 0x1000>;
+                               reg = <0 0x1780b000 0x1000>;
 
                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3482,7 +3482,7 @@
                        };
 
                        frame@1780d000 {
-                               reg = <0 0x1780d000 0 0x1000>;
+                               reg = <0 0x1780d000 0x1000>;
 
                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;