net: phy: dp83826: Add support for phy-mode configuration

The TI DP83826 PHY can operate in either MII mode or RMII mode.
By default, it is configured by straps.
It can also be configured by writing to the bit 5 of register 0x17 - RMII
and Status Register (RCSR).

When phydev->interface is rmii, rmii mode must be enabled, otherwise
mii mode must be set.
This prevents misconfiguration of hw straps.

Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 30f2616ab1c261033fe93253b33fb50d8f6cfd51..2d8275e59dcc20a49da9647e124a18f25eb61ced 100644 (file)
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -100,6 +100,7 @@
 #define DP83822_WOL_CLR_INDICATION BIT(11)
 
 /* RCSR bits */
+#define DP83822_RMII_MODE_EN   BIT(5)
 #define DP83822_RGMII_MODE_EN  BIT(9)
 #define DP83822_RX_CLK_SHIFT   BIT(12)
 #define DP83822_TX_CLK_SHIFT   BIT(11)
@@ -500,6 +501,16 @@ static int dp83826_config_init(struct phy_device *phydev)
        u16 val, mask;
        int ret;
 
+       if (phydev->interface == PHY_INTERFACE_MODE_RMII)
+               ret = phy_set_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
+                                      DP83822_RMII_MODE_EN);
+       else
+               ret = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
+                                        DP83822_RMII_MODE_EN);
+
+       if (ret)
+               return ret;
+
        if (dp83822->cfg_dac_minus != DP83826_CFG_DAC_MINUS_DEFAULT) {
                val = FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDI_MASK, dp83822->cfg_dac_minus) |
                      FIELD_PREP(DP83826_VOD_CFG1_MINUS_MDIX_MASK,