drm/amd/display: Add clear DCC and Tiling callback for DCN

Introduce the DCC and Tiling reset callback to all DCN versions that can
call it.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index aa4184dd0e53ea371619cbc15ebbbf62baecdc4d..691b4a68d8ac3ad3134acf0fcfa095901de2a5b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -291,17 +291,8 @@ void dc_plane_force_dcc_and_tiling_disable(struct dc_plane_state *plane_state,
                        continue;
 
                if (dc->ctx->dce_version >= DCE_VERSION_MAX) {
-                       struct hubp *hubp = pipe_ctx->plane_res.hubp;
-                       if (!hubp)
-                               continue;
-                       /* if framebuffer is tiled, disable tiling */
-                       if (clear_tiling && hubp->funcs->hubp_clear_tiling)
-                               hubp->funcs->hubp_clear_tiling(hubp);
-
-                       /* force page flip to see the new content of the framebuffer */
-                       hubp->funcs->hubp_program_surface_flip_and_addr(hubp,
-                                                                       &plane_state->address,
-                                                                       true);
+                       if (dc->hwss.clear_surface_dcc_and_tiling)
+                               dc->hwss.clear_surface_dcc_and_tiling(pipe_ctx, plane_state, clear_tiling);
                } else {
                        struct mem_input *mi = pipe_ctx->plane_res.mi;
                        if (!mi)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
index 5e51e1761707de45ed55f37c9637177da28a6b51..079c226c1097ff0f0c21ccf69d89261431cc519b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
@@ -40,6 +40,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .update_plane_addr = dcn10_update_plane_addr,
        .update_dchub = dcn10_update_dchub,
        .update_pending_status = dcn10_update_pending_status,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .program_output_csc = dcn10_program_output_csc,
        .enable_accelerated_mode = dce110_enable_accelerated_mode,
        .enable_timing_synchronization = dcn10_enable_timing_synchronization,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
index 32707b344f0b68e8b8da39c786ffcb14e2a621c6..ad253c586ea1ac78649b14e5aa69ca40e6c3f05c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
@@ -36,6 +36,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
index 78351408e864225feedaa3074160a732f440c80c..dec57fb4c05c971d5160a646892bcaa36167645b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
@@ -36,6 +36,7 @@ static const struct hw_sequencer_funcs dcn201_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
        .update_plane_addr = dcn201_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
index e044e9e0a3a17a6b5dd915b18428d4a29bcb8e65..c7701a8b574aa390ed696ac6213aea55d76736c1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
@@ -37,6 +37,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index c32764aef8840062c4099c87e16bbce4378e6f22..2ac5d54d162693cd3d5c2546d7725bc8c7e42bee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -37,6 +37,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
index dcb27cdbce7319ea8c513fa6deeaa963c62d3a1f..8d7ceb7b32b86c2b224488695fce635065c14213 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
@@ -39,6 +39,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index fb2ffb6379317a06220961515edde964fa659229..556f4fe57eda79637ac537da50d0a93c63965cb7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -40,6 +40,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 21ef03a76229a18f81b8d7b4498f10ecde7fc9da..f5112742edf9b4e7722bbbbb041e81551644e121 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -42,6 +42,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index e4d149eff10f5d78556f6b52e51a721890b6f648..b971356d30b18c2e8c570063adf6d95b4d6cae70 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -39,6 +39,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index c7acaf97974c4659a7977686fdf2b491980eb617..6a82a865209cb4330938992d758abe0c4dea9e59 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -44,6 +44,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 4f73e7f551acac906ccc431de8d044e803b0b65f..902a96940a015b5139be2cde0dffb4962045e5ee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -43,6 +43,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index a4e3501fadbbe08070d3b797d1516d74568d647a..fe7aceb2f5104a94938db1f8e9b8c121c24a2868 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -18,6 +18,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
        .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
        .apply_ctx_for_surface = NULL,
        .program_front_end_for_ctx = dcn401_program_front_end_for_ctx,
+       .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling,
        .wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
        .post_unlock_program_front_end = dcn401_post_unlock_program_front_end,
        .update_plane_addr = dcn20_update_plane_addr,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index a7d66cfd93c9116bdc75ad1918a8a90e7e01e4fd..599fa41fd75f41739f5f090b266611c357b181f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -240,6 +240,7 @@ struct hw_sequencer_funcs {
                struct pipe_ctx *pipe_ctx, bool enableTripleBuffer);
        void (*update_pending_status)(struct pipe_ctx *pipe_ctx);
        void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable);
+       void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling);
 
        /* Pipe Lock Related */
        void (*pipe_control_lock)(struct dc *dc,