Merge tag 'drm-intel-gt-next-2023-03-16' of git://anongit.freedesktop.org/drm/drm...

Driver Changes:

- Fix issue #6333: "list_add corruption" and full system lockup from
  performance monitoring (Janusz)
- Give the punit time to settle before fatally failing (Aravind, Chris)
- Don't use stolen memory or BAR for ring buffers on LLC platforms (John)
- Add missing ecodes and correct timeline seqno on GuC error captures (John)
- Make sure DSM size has correct 1MiB granularity on Gen12+ (Nirmoy,
  Lucas)
- Fix potential SSEU max_subslices array-index-out-of-bounds access on Gen11 (Andrea)
- Whitelist COMMON_SLICE_CHICKEN3 for UMD access on Gen12+ (Matt R.)
- Apply Wa_1408615072/Wa_1407596294 correctly on Gen11 (Matt R)
- Apply LNCF/LBCF workarounds correctly on XeHP SDV/PVC/DG2 (Matt R)
- Implement Wa_1606376872 for Xe_LP (Gustavo)
- Consider GSI offset when doing MCR lookups on Meteorlake+ (Matt R.)
- Add engine TLB invalidation for Meteorlake (Matt R.)
- Fix GSC Driver-FLR completion on Meteorlake (Alan)
- Fix GSC races on driver load/unload on Meteorlake+ (Daniele)
- Disable MC6 for MTL A step (Badal)

- Consolidate TLB invalidation flow (Tvrtko)
- Improve debug GuC/HuC debug messages (Michal Wa., John)
- Move fd_install after last use of fence (Rob)
- Initialize the obj flags for shmem objects (Aravind)
- Fix missing debug object activation (Nirmoy)
- Probe lmem before the stolen portion (Matt A)
- Improve clean up of GuC busyness stats worker (John)
- Fix missing return code checks in GuC submission init (John)
- Annotate two more workaround/tuning registers as MCR on PVC (Matt R)
- Fix GEN8_MISCCPCTL definition and remove unused INF_UNIT_LEVEL_CLKGATE (Lucas)
- Use sysfs_emit() and sysfs_emit_at() (Nirmoy)
- Make kobj_type structures constant (Thomas W.)
- make kobj attributes const on gt/ (Jani)
- Remove the unused virtualized start hack on buddy allocator (Matt A)
- Remove redundant check for DG1 (Lucas)
- Move DG2 tuning to the right function (Lucas)
- Rename dev_priv to i915 for private data naming consistency in gt/ (Andi)
- Remove unnecessary whitelisting of CS_CTX_TIMESTAMP on Xe_HP platforms (Matt R.)
-

- Escape wildcard in method names in kerneldoc (Bagas)
- Selftest improvements (Chris, Jonathan, Tvrtko, Anshuman, Tejas)
- Fix sparse warnings (Jani)

[airlied: fix unused variable in intel_workarounds]
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZBMSb42yjjzczRhj@jlahtine-mobl.ger.corp.intel.com

diff --combined drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 90a967374b1a5e55b92190aa3ae7f09fc4535015,7ab9e98bcbd21d2257cd46e4449da4e7b828c5a1..d8e06e783e30f45b00f913682c0377a58cd11cd4
--- 1/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
--- 2/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@@ -110,7 -110,9 +110,7 @@@ static int adjust_stolen(struct drm_i91
                else
                        ggtt_start &= PGTBL_ADDRESS_LO_MASK;
  
 -              ggtt_res =
 -                      (struct resource) DEFINE_RES_MEM(ggtt_start,
 -                                                       ggtt_total_entries(ggtt) * 4);
 +              ggtt_res = DEFINE_RES_MEM(ggtt_start, ggtt_total_entries(ggtt) * 4);
  
                if (ggtt_res.start >= stolen[0].start && ggtt_res.start < stolen[0].end)
                        stolen[0].end = ggtt_res.start;
@@@ -209,7 -211,7 +209,7 @@@ static void g4x_get_stolen_reserved(str
                                        IS_GM45(i915) ?
                                        CTG_STOLEN_RESERVED :
                                        ELK_STOLEN_RESERVED);
 -      resource_size_t stolen_top = i915->dsm.end + 1;
 +      resource_size_t stolen_top = i915->dsm.stolen.end + 1;
  
        drm_dbg(&i915->drm, "%s_STOLEN_RESERVED = %08x\n",
                IS_GM45(i915) ? "CTG" : "ELK", reg_val);
@@@ -274,7 -276,7 +274,7 @@@ static void vlv_get_stolen_reserved(str
                                    resource_size_t *size)
  {
        u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
 -      resource_size_t stolen_top = i915->dsm.end + 1;
 +      resource_size_t stolen_top = i915->dsm.stolen.end + 1;
  
        drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
  
@@@ -363,7 -365,7 +363,7 @@@ static void bdw_get_stolen_reserved(str
                                    resource_size_t *size)
  {
        u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
 -      resource_size_t stolen_top = i915->dsm.end + 1;
 +      resource_size_t stolen_top = i915->dsm.stolen.end + 1;
  
        drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
  
@@@ -412,7 -414,7 +412,7 @@@ static void icl_get_stolen_reserved(str
  }
  
  /*
 - * Initialize i915->dsm_reserved to contain the reserved space within the Data
 + * Initialize i915->dsm.reserved to contain the reserved space within the Data
   * Stolen Memory. This is a range on the top of DSM that is reserved, not to
   * be used by driver, so must be excluded from the region passed to the
   * allocator later. In the spec this is also called as WOPCM.
@@@ -428,7 -430,7 +428,7 @@@ static int init_reserved_stolen(struct 
        resource_size_t reserved_size;
        int ret = 0;
  
 -      stolen_top = i915->dsm.end + 1;
 +      stolen_top = i915->dsm.stolen.end + 1;
        reserved_base = stolen_top;
        reserved_size = 0;
  
@@@ -469,12 -471,13 +469,12 @@@
                goto bail_out;
        }
  
 -      i915->dsm_reserved =
 -              (struct resource)DEFINE_RES_MEM(reserved_base, reserved_size);
 +      i915->dsm.reserved = DEFINE_RES_MEM(reserved_base, reserved_size);
  
 -      if (!resource_contains(&i915->dsm, &i915->dsm_reserved)) {
 +      if (!resource_contains(&i915->dsm.stolen, &i915->dsm.reserved)) {
                drm_err(&i915->drm,
                        "Stolen reserved area %pR outside stolen memory %pR\n",
 -                      &i915->dsm_reserved, &i915->dsm);
 +                      &i915->dsm.reserved, &i915->dsm.stolen);
                ret = -EINVAL;
                goto bail_out;
        }
@@@ -482,7 -485,8 +482,7 @@@
        return 0;
  
  bail_out:
 -      i915->dsm_reserved =
 -              (struct resource)DEFINE_RES_MEM(reserved_base, 0);
 +      i915->dsm.reserved = DEFINE_RES_MEM(reserved_base, 0);
  
        return ret;
  }
@@@ -513,27 -517,27 +513,27 @@@ static int i915_gem_init_stolen(struct 
        if (request_smem_stolen(i915, &mem->region))
                return -ENOSPC;
  
 -      i915->dsm = mem->region;
 +      i915->dsm.stolen = mem->region;
  
        if (init_reserved_stolen(i915))
                return -ENOSPC;
  
        /* Exclude the reserved region from driver use */
 -      mem->region.end = i915->dsm_reserved.start - 1;
 +      mem->region.end = i915->dsm.reserved.start - 1;
        mem->io_size = min(mem->io_size, resource_size(&mem->region));
  
 -      i915->stolen_usable_size = resource_size(&mem->region);
 +      i915->dsm.usable_size = resource_size(&mem->region);
  
        drm_dbg(&i915->drm,
                "Memory reserved for graphics device: %lluK, usable: %lluK\n",
 -              (u64)resource_size(&i915->dsm) >> 10,
 -              (u64)i915->stolen_usable_size >> 10);
 +              (u64)resource_size(&i915->dsm.stolen) >> 10,
 +              (u64)i915->dsm.usable_size >> 10);
  
 -      if (i915->stolen_usable_size == 0)
 +      if (i915->dsm.usable_size == 0)
                return -ENOSPC;
  
        /* Basic memrange allocator for stolen space. */
 -      drm_mm_init(&i915->mm.stolen, 0, i915->stolen_usable_size);
 +      drm_mm_init(&i915->mm.stolen, 0, i915->dsm.usable_size);
  
        return 0;
  }
@@@ -583,7 -587,7 +583,7 @@@ i915_pages_create_for_stolen(struct drm
        struct sg_table *st;
        struct scatterlist *sg;
  
 -      GEM_BUG_ON(range_overflows(offset, size, resource_size(&i915->dsm)));
 +      GEM_BUG_ON(range_overflows(offset, size, resource_size(&i915->dsm.stolen)));
  
        /* We hide that we have no struct page backing our stolen object
         * by wrapping the contiguous physical allocation with a fake
@@@ -603,7 -607,7 +603,7 @@@
        sg->offset = 0;
        sg->length = size;
  
 -      sg_dma_address(sg) = (dma_addr_t)i915->dsm.start + offset;
 +      sg_dma_address(sg) = (dma_addr_t)i915->dsm.stolen.start + offset;
        sg_dma_len(sg) = size;
  
        return st;
@@@ -909,7 -913,7 +909,7 @@@ i915_gem_stolen_lmem_setup(struct drm_i
                dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
                if (WARN_ON(lmem_size < dsm_base))
                        return ERR_PTR(-ENODEV);
-               dsm_size = lmem_size - dsm_base;
+               dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
        }
  
        io_size = dsm_size;

diff --combined drivers/gpu/drm/i915/gt/intel_gt.c
index f4f694f1290754b5dba9876828fab5c62201d87c,89ccb95e146ca74aa080fc724f18dab2262961f7..256cecf99dd12eaef558bcdb39eeaf7ee1eefcce
--- 1/drivers/gpu/drm/i915/gt/intel_gt.c
--- 2/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@@ -28,6 -28,7 +28,6 @@@
  #include "intel_migrate.h"
  #include "intel_mocs.h"
  #include "intel_pci_config.h"
 -#include "intel_pm.h"
  #include "intel_rc6.h"
  #include "intel_renderstate.h"
  #include "intel_rps.h"
@@@ -783,6 -784,29 +783,29 @@@ void intel_gt_driver_unregister(struct 
        intel_rps_driver_unregister(&gt->rps);
        intel_gsc_fini(&gt->gsc);
  
+       /*
+        * If we unload the driver and wedge before the GSC worker is complete,
+        * the worker will hit an error on its submission to the GSC engine and
+        * then exit. This is hard to hit for a user, but it is reproducible
+        * with skipping selftests. The error is handled gracefully by the
+        * worker, so there are no functional issues, but we still end up with
+        * an error message in dmesg, which is something we want to avoid as
+        * this is a supported scenario. We could modify the worker to better
+        * handle a wedging occurring during its execution, but that gets
+        * complicated for a couple of reasons:
+        * - We do want the error on runtime wedging, because there are
+        *   implications for subsystems outside of GT (i.e., PXP, HDCP), it's
+        *   only the error on driver unload that we want to silence.
+        * - The worker is responsible for multiple submissions (GSC FW load,
+        *   HuC auth, SW proxy), so all of those will have to be adapted to
+        *   handle the wedged_on_fini scenario.
+        * Therefore, it's much simpler to just wait for the worker to be done
+        * before wedging on driver removal, also considering that the worker
+        * will likely already be idle in the great majority of non-selftest
+        * scenarios.
+        */
+       intel_gsc_uc_flush_work(&gt->uc.gsc);
+ 
        /*
         * Upon unregistering the device to prevent any new users, cancel
         * all in-flight requests so that we can quickly unbind the active
@@@ -981,35 -1005,6 +1004,6 @@@ void intel_gt_info_print(const struct i
        intel_sseu_dump(&info->sseu, p);
  }
  
- struct reg_and_bit {
-       union {
-               i915_reg_t reg;
-               i915_mcr_reg_t mcr_reg;
-       };
-       u32 bit;
- };
- 
- static struct reg_and_bit
- get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8,
-               const i915_reg_t *regs, const unsigned int num)
- {
-       const unsigned int class = engine->class;
-       struct reg_and_bit rb = { };
- 
-       if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))
-               return rb;
- 
-       rb.reg = regs[class];
-       if (gen8 && class == VIDEO_DECODE_CLASS)
-               rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */
-       else
-               rb.bit = engine->instance;
- 
-       rb.bit = BIT(rb.bit);
- 
-       return rb;
- }
- 
  /*
   * HW architecture suggest typical invalidation time at 40us,
   * with pessimistic cases up to 100us and a recommendation to
@@@ -1023,14 -1018,20 +1017,20 @@@
   * but are now considered MCR registers.  Since they exist within a GAM range,
   * the primary instance of the register rolls up the status from each unit.
   */
- static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb)
+ static int wait_for_invalidate(struct intel_engine_cs *engine)
  {
-       if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
-               return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0,
+       if (engine->tlb_inv.mcr)
+               return intel_gt_mcr_wait_for_reg(engine->gt,
+                                                engine->tlb_inv.reg.mcr_reg,
+                                                engine->tlb_inv.done,
+                                                0,
                                                 TLB_INVAL_TIMEOUT_US,
                                                 TLB_INVAL_TIMEOUT_MS);
        else
-               return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0,
+               return __intel_wait_for_register_fw(engine->gt->uncore,
+                                                   engine->tlb_inv.reg.reg,
+                                                   engine->tlb_inv.done,
+                                                   0,
                                                    TLB_INVAL_TIMEOUT_US,
                                                    TLB_INVAL_TIMEOUT_MS,
                                                    NULL);
@@@ -1038,62 -1039,14 +1038,14 @@@
  
  static void mmio_invalidate_full(struct intel_gt *gt)
  {
-       static const i915_reg_t gen8_regs[] = {
-               [RENDER_CLASS]                  = GEN8_RTCR,
-               [VIDEO_DECODE_CLASS]            = GEN8_M1TCR, /* , GEN8_M2TCR */
-               [VIDEO_ENHANCEMENT_CLASS]       = GEN8_VTCR,
-               [COPY_ENGINE_CLASS]             = GEN8_BTCR,
-       };
-       static const i915_reg_t gen12_regs[] = {
-               [RENDER_CLASS]                  = GEN12_GFX_TLB_INV_CR,
-               [VIDEO_DECODE_CLASS]            = GEN12_VD_TLB_INV_CR,
-               [VIDEO_ENHANCEMENT_CLASS]       = GEN12_VE_TLB_INV_CR,
-               [COPY_ENGINE_CLASS]             = GEN12_BLT_TLB_INV_CR,
-               [COMPUTE_CLASS]                 = GEN12_COMPCTX_TLB_INV_CR,
-       };
-       static const i915_mcr_reg_t xehp_regs[] = {
-               [RENDER_CLASS]                  = XEHP_GFX_TLB_INV_CR,
-               [VIDEO_DECODE_CLASS]            = XEHP_VD_TLB_INV_CR,
-               [VIDEO_ENHANCEMENT_CLASS]       = XEHP_VE_TLB_INV_CR,
-               [COPY_ENGINE_CLASS]             = XEHP_BLT_TLB_INV_CR,
-               [COMPUTE_CLASS]                 = XEHP_COMPCTX_TLB_INV_CR,
-       };
        struct drm_i915_private *i915 = gt->i915;
        struct intel_uncore *uncore = gt->uncore;
        struct intel_engine_cs *engine;
        intel_engine_mask_t awake, tmp;
        enum intel_engine_id id;
-       const i915_reg_t *regs;
-       unsigned int num = 0;
        unsigned long flags;
  
-       /*
-        * New platforms should not be added with catch-all-newer (>=)
-        * condition so that any later platform added triggers the below warning
-        * and in turn mandates a human cross-check of whether the invalidation
-        * flows have compatible semantics.
-        *
-        * For instance with the 11.00 -> 12.00 transition three out of five
-        * respective engine registers were moved to masked type. Then after the
-        * 12.00 -> 12.50 transition multi cast handling is required too.
-        */
- 
-       if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
-           GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
-               regs = NULL;
-               num = ARRAY_SIZE(xehp_regs);
-       } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
-                  GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
-               regs = gen12_regs;
-               num = ARRAY_SIZE(gen12_regs);
-       } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) {
-               regs = gen8_regs;
-               num = ARRAY_SIZE(gen8_regs);
-       } else if (GRAPHICS_VER(i915) < 8) {
-               return;
-       }
- 
-       if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))
+       if (GRAPHICS_VER(i915) < 8)
                return;
  
        intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@@ -1103,33 -1056,18 +1055,18 @@@
  
        awake = 0;
        for_each_engine(engine, gt, id) {
-               struct reg_and_bit rb;
- 
                if (!intel_engine_pm_is_awake(engine))
                        continue;
  
-               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
-                       u32 val = BIT(engine->instance);
- 
-                       if (engine->class == VIDEO_DECODE_CLASS ||
-                           engine->class == VIDEO_ENHANCEMENT_CLASS ||
-                           engine->class == COMPUTE_CLASS)
-                               val = _MASKED_BIT_ENABLE(val);
+               if (engine->tlb_inv.mcr)
                        intel_gt_mcr_multicast_write_fw(gt,
-                                                       xehp_regs[engine->class],
-                                                       val);
-               } else {
-                       rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
-                       if (!i915_mmio_reg_offset(rb.reg))
-                               continue;
- 
-                       if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
-                           engine->class == VIDEO_ENHANCEMENT_CLASS ||
-                           engine->class == COMPUTE_CLASS))
-                               rb.bit = _MASKED_BIT_ENABLE(rb.bit);
- 
-                       intel_uncore_write_fw(uncore, rb.reg, rb.bit);
-               }
+                                                       engine->tlb_inv.reg.mcr_reg,
+                                                       engine->tlb_inv.request);
+               else
+                       intel_uncore_write_fw(uncore,
+                                             engine->tlb_inv.reg.reg,
+                                             engine->tlb_inv.request);
+ 
                awake |= engine->mask;
        }
  
@@@ -1148,17 -1086,9 +1085,9 @@@
        intel_gt_mcr_unlock(gt, flags);
  
        for_each_engine_masked(engine, gt, awake, tmp) {
-               struct reg_and_bit rb;
- 
-               if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
-                       rb.mcr_reg = xehp_regs[engine->class];
-                       rb.bit = BIT(engine->instance);
-               } else {
-                       rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
-               }
- 
-               if (wait_for_invalidate(gt, rb))
-                       gt_err_ratelimited(gt, "%s TLB invalidation did not complete in %ums!\n",
+               if (wait_for_invalidate(engine))
+                       gt_err_ratelimited(gt,
+                                          "%s TLB invalidation did not complete in %ums!\n",
                                           engine->name, TLB_INVAL_TIMEOUT_MS);
        }
  
@@@ -1204,3 -1134,7 +1133,7 @@@ unlock
                mutex_unlock(&gt->tlb.invalidate_lock);
        }
  }
+ 
+ #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+ #include "selftest_tlb.c"
+ #endif

diff --combined drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 85ae7dc079f28195209a21952c04a77e1b6e59e8,56b993f6e7dc9337aa98d24b08748606d9e8a922..e02cb90723ae03c7c3a90b50ac7aa6f87175472b
--- 1/drivers/gpu/drm/i915/gt/intel_gt_pm.c
--- 2/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@@ -17,34 -17,14 +17,13 @@@
  #include "intel_gt_print.h"
  #include "intel_gt_requests.h"
  #include "intel_llc.h"
 -#include "intel_pm.h"
  #include "intel_rc6.h"
  #include "intel_rps.h"
  #include "intel_wakeref.h"
- #include "intel_pcode.h"
  #include "pxp/intel_pxp_pm.h"
  
  #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
  
- static void mtl_media_busy(struct intel_gt *gt)
- {
-       /* Wa_14017073508: mtl */
-       if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
-           gt->type == GT_MEDIA)
-               snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
-                                 PCODE_MBOX_GT_STATE_MEDIA_BUSY,
-                                 PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
- }
- 
- static void mtl_media_idle(struct intel_gt *gt)
- {
-       /* Wa_14017073508: mtl */
-       if (IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0) &&
-           gt->type == GT_MEDIA)
-               snb_pcode_write_p(gt->uncore, PCODE_MBOX_GT_STATE,
-                                 PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY,
-                                 PCODE_MBOX_GT_STATE_DOMAIN_MEDIA, 0);
- }
- 
  static void user_forcewake(struct intel_gt *gt, bool suspend)
  {
        int count = atomic_read(&gt->user_wakeref);
@@@ -92,9 -72,6 +71,6 @@@ static int __gt_unpark(struct intel_wak
  
        GT_TRACE(gt, "\n");
  
-       /* Wa_14017073508: mtl */
-       mtl_media_busy(gt);
- 
        /*
         * It seems that the DMC likes to transition between the DC states a lot
         * when there are no connected displays (no active power domains) during
@@@ -144,9 -121,6 +120,6 @@@ static int __gt_park(struct intel_waker
        GEM_BUG_ON(!wakeref);
        intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
  
-       /* Wa_14017073508: mtl */
-       mtl_media_idle(gt);
- 
        return 0;
  }
  

diff --combined drivers/gpu/drm/i915/gt/intel_gt_regs.h
index df07e1e799e3f7a6513fc28942f46656dcdf45fd,97a60941eee5d8935cd5c9f65e127db95dd94677..4aecb5a7b6318e6986c4b74d139dd9f8880fec9f
--- 1/drivers/gpu/drm/i915/gt/intel_gt_regs.h
--- 2/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@@ -9,6 -9,8 +9,6 @@@
  #include "i915_reg_defs.h"
  #include "display/intel_display_reg_defs.h"   /* VLV_DISPLAY_BASE */
  
 -#define MCR_REG(offset)       ((const i915_mcr_reg_t){ .reg = (offset) })
 -
  /*
   * The perf control registers are technically multicast registers, but the
   * driver never needs to read/write them directly; we only use them to build
@@@ -478,6 -480,9 +478,9 @@@
  #define   HDC_FORCE_NON_COHERENT              (1 << 4)
  #define   HDC_BARRIER_PERFORMANCE_DISABLE     (1 << 10)
  
+ #define COMMON_SLICE_CHICKEN4                 _MMIO(0x7300)
+ #define   DISABLE_TDC_LOAD_BALANCING_CALC     REG_BIT(6)
+ 
  #define GEN8_HDC_CHICKEN1                     _MMIO(0x7304)
  
  #define GEN11_COMMON_SLICE_CHICKEN3           _MMIO(0x7304)
@@@ -767,9 -772,6 +770,6 @@@
  #define GEN10_DFR_RATIO_EN_AND_CHICKEN                MCR_REG(0x9550)
  #define   DFR_DISABLE                         (1 << 9)
  
- #define INF_UNIT_LEVEL_CLKGATE                        MCR_REG(0x9560)
- #define   CGPSF_CLKGATE_DIS                   (1 << 3)
- 
  #define MICRO_BP0_0                           _MMIO(0x9800)
  #define MICRO_BP0_2                           _MMIO(0x9804)
  #define MICRO_BP0_1                           _MMIO(0x9808)
@@@ -1091,6 -1093,7 +1091,7 @@@
  #define XEHP_BLT_TLB_INV_CR                   MCR_REG(0xcee4)
  #define GEN12_COMPCTX_TLB_INV_CR              _MMIO(0xcf04)
  #define XEHP_COMPCTX_TLB_INV_CR                       MCR_REG(0xcf04)
+ #define XELPMP_GSC_TLB_INV_CR                 _MMIO(0xcf04)   /* media GT only */
  
  #define XEHP_MERT_MOD_CTRL                    MCR_REG(0xcf28)
  #define RENDER_MOD_CTRL                               MCR_REG(0xcf2c)

diff --combined drivers/gpu/drm/i915/gt/intel_rc6.c
index 5c91622dfca420bc37c7c200b9e20927a14ca720,6184fcc169877d6287150ec24a78286c1d0bf0a6..f4150f61f39c0be7cae48e67fc3430a7640ce0c1
--- 1/drivers/gpu/drm/i915/gt/intel_rc6.c
--- 2/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@@ -301,7 -301,7 +301,7 @@@ static int chv_rc6_init(struct intel_rc
        pcbr = intel_uncore_read(uncore, VLV_PCBR);
        if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
                drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
 -              paddr = i915->dsm.end + 1 - pctx_size;
 +              paddr = i915->dsm.stolen.end + 1 - pctx_size;
                GEM_BUG_ON(paddr > U32_MAX);
  
                pctx_paddr = (paddr & ~4095);
@@@ -325,7 -325,7 +325,7 @@@ static int vlv_rc6_init(struct intel_rc
                /* BIOS set it up already, grab the pre-alloc'd space */
                resource_size_t pcbr_offset;
  
 -              pcbr_offset = (pcbr & ~4095) - i915->dsm.start;
 +              pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start;
                pctx = i915_gem_object_create_region_at(i915->mm.stolen_region,
                                                        pcbr_offset,
                                                        pctx_size,
@@@ -354,10 -354,10 +354,10 @@@
        }
  
        GEM_BUG_ON(range_overflows_end_t(u64,
 -                                       i915->dsm.start,
 +                                       i915->dsm.stolen.start,
                                         pctx->stolen->start,
                                         U32_MAX));
 -      pctx_paddr = i915->dsm.start + pctx->stolen->start;
 +      pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start;
        intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
  
  out:
@@@ -448,8 -448,8 +448,8 @@@ static bool bxt_check_bios_rc6_setup(st
         */
        rc6_ctx_base =
                intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
 -      if (!(rc6_ctx_base >= i915->dsm_reserved.start &&
 -            rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) {
 +      if (!(rc6_ctx_base >= i915->dsm.reserved.start &&
 +            rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) {
                drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");
                enable_rc6 = false;
        }
@@@ -486,6 -486,7 +486,7 @@@
  static bool rc6_supported(struct intel_rc6 *rc6)
  {
        struct drm_i915_private *i915 = rc6_to_i915(rc6);
+       struct intel_gt *gt = rc6_to_gt(rc6);
  
        if (!HAS_RC6(i915))
                return false;
@@@ -500,6 -501,13 +501,13 @@@
                drm_notice(&i915->drm,
                           "RC6 and powersaving disabled by BIOS\n");
                return false;
+       }
+ 
+       if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
+           gt->type == GT_MEDIA) {
+               drm_notice(&i915->drm,
+                          "Media RC6 disabled on A step\n");
+               return false;
        }
  
        return true;

diff --combined drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8859eb118510cd5e20ed6c71b30cbb0d6481067c,60e9cf273c5ef6c0939a24fd6213b8a397d02979..e7ee24bcad893761e4bfa8cfc658c0d30851567c
--- 1/drivers/gpu/drm/i915/gt/intel_workarounds.c
--- 2/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -743,9 -743,13 +743,13 @@@ static void gen12_ctx_workarounds_init(
               FF_MODE2_GS_TIMER_224,
               0, false);
  
-       if (!IS_DG1(i915))
+       if (!IS_DG1(i915)) {
                /* Wa_1806527549 */
                wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
+ 
+               /* Wa_1606376872 */
+               wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
+       }
  }
  
  static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
@@@ -1469,24 -1473,51 +1473,18 @@@ gen12_gt_workarounds_init(struct intel_
        wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
  }
  
 -static void
 -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 -{
 -      struct drm_i915_private *i915 = gt->i915;
 -
 -      gen12_gt_workarounds_init(gt, wal);
 -
 -      /* Wa_1409420604:tgl */
 -      if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 -              wa_mcr_write_or(wal,
 -                              SUBSLICE_UNIT_LEVEL_CLKGATE2,
 -                              CPSSUNIT_CLKGATE_DIS);
 -
 -      /* Wa_1607087056:tgl also know as BUG:1409180338 */
 -      if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 -              wa_write_or(wal,
 -                          GEN11_SLICE_UNIT_LEVEL_CLKGATE,
 -                          L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 -
 -      /* Wa_1408615072:tgl[a0] */
 -      if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 -              wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
 -                          VSUNIT_CLKGATE_DIS_TGL);
 -}
 -
  static void
  dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
--      struct drm_i915_private *i915 = gt->i915;
--
        gen12_gt_workarounds_init(gt, wal);
  
 -      /* Wa_1607087056:dg1 */
 -      if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
 -              wa_write_or(wal,
 -                          GEN11_SLICE_UNIT_LEVEL_CLKGATE,
 -                          L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 -
        /* Wa_1409420604:dg1 */
-       if (IS_DG1(i915))
-               wa_mcr_write_or(wal,
-                               SUBSLICE_UNIT_LEVEL_CLKGATE2,
-                               CPSSUNIT_CLKGATE_DIS);
+       wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
+                       CPSSUNIT_CLKGATE_DIS);
  
        /* Wa_1408615072:dg1 */
        /* Empirical testing shows this register is unaffected by engine reset. */
-       if (IS_DG1(i915))
-               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-                           VSUNIT_CLKGATE_DIS_TGL);
+       wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
  }
  
  static void
@@@ -1499,6 -1530,12 +1497,12 @@@ xehpsdv_gt_workarounds_init(struct inte
        /* Wa_1409757795:xehpsdv */
        wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
  
+       /* Wa_18011725039:xehpsdv */
+       if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
+               wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
+               wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
+       }
+ 
        /* Wa_16011155590:xehpsdv */
        if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
                wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
@@@ -1548,6 -1585,9 +1552,9 @@@
        /* Wa_14014368820:xehpsdv */
        wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
                        INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
+ 
+       /* Wa_14010670810:xehpsdv */
+       wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
  }
  
  static void
@@@ -1650,13 -1690,6 +1657,6 @@@ dg2_gt_workarounds_init(struct intel_g
        /* Wa_14014830051:dg2 */
        wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
  
-       /*
-        * The following are not actually "workarounds" but rather
-        * recommended tuning settings documented in the bspec's
-        * performance guide section.
-        */
-       wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
- 
        /* Wa_14015795083 */
        wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
  
@@@ -1669,6 -1702,9 +1669,9 @@@
        /* Wa_1509235366:dg2 */
        wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
                        INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
+ 
+       /* Wa_14010648519:dg2 */
+       wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
  }
  
  static void
@@@ -1684,6 -1720,9 +1687,9 @@@ pvc_gt_workarounds_init(struct intel_g
        wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
        wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
        wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ 
+       /* Wa_16016694945 */
+       wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
  }
  
  static void
@@@ -1724,11 -1763,38 +1730,38 @@@ xelpmp_gt_workarounds_init(struct intel
        debug_dump_steering(gt);
  }
  
+ /*
+  * The bspec performance guide has recommended MMIO tuning settings.  These
+  * aren't truly "workarounds" but we want to program them through the
+  * workaround infrastructure to make sure they're (re)applied at the proper
+  * times.
+  *
+  * The programming in this function is for settings that persist through
+  * engine resets and also are not part of any engine's register state context.
+  * I.e., settings that only need to be re-applied in the event of a full GT
+  * reset.
+  */
+ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
+ {
+       if (IS_PONTEVECCHIO(gt->i915)) {
+               wa_mcr_write(wal, XEHPC_L3SCRUB,
+                            SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+               wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
+       }
+ 
+       if (IS_DG2(gt->i915)) {
+               wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+               wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+       }
+ }
+ 
  static void
  gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
  {
        struct drm_i915_private *i915 = gt->i915;
  
+       gt_tuning_settings(gt, wal);
+ 
        if (gt->type == GT_MEDIA) {
                if (MEDIA_VER(i915) >= 13)
                        xelpmp_gt_workarounds_init(gt, wal);
@@@ -1748,6 -1814,8 +1781,6 @@@
                xehpsdv_gt_workarounds_init(gt, wal);
        else if (IS_DG1(i915))
                dg1_gt_workarounds_init(gt, wal);
 -      else if (IS_TIGERLAKE(i915))
 -              tgl_gt_workarounds_init(gt, wal);
        else if (GRAPHICS_VER(i915) == 12)
                gen12_gt_workarounds_init(gt, wal);
        else if (GRAPHICS_VER(i915) == 11)
@@@ -2154,23 -2222,34 +2187,20 @@@ static void tgl_whitelist_build(struct 
  
                /* Wa_1806527549:tgl */
                whitelist_reg(w, HIZ_CHICKEN);
+ 
+               /* Required by recommended tuning setting (not a workaround) */
+               whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
+ 
                break;
        default:
                break;
        }
  }
  
- static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
 -static void dg1_whitelist_build(struct intel_engine_cs *engine)
--{
-       allow_read_ctx_timestamp(engine);
 -      struct i915_wa_list *w = &engine->whitelist;
 -
 -      tgl_whitelist_build(engine);
 -
 -      /* GEN:BUG:1409280441:dg1 */
 -      if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
 -          (engine->class == RENDER_CLASS ||
 -           engine->class == COPY_ENGINE_CLASS))
 -              whitelist_reg_ext(w, RING_ID(engine->mmio_base),
 -                                RING_FORCE_TO_NONPRIV_ACCESS_RD);
--}
--
  static void dg2_whitelist_build(struct intel_engine_cs *engine)
  {
        struct i915_wa_list *w = &engine->whitelist;
  
-       allow_read_ctx_timestamp(engine);
- 
        switch (engine->class) {
        case RENDER_CLASS:
                /*
@@@ -2187,6 -2266,9 +2217,9 @@@
                                          RING_FORCE_TO_NONPRIV_ACCESS_RD |
                                          RING_FORCE_TO_NONPRIV_RANGE_4);
  
+               /* Required by recommended tuning setting (not a workaround) */
+               whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
+ 
                break;
        case COMPUTE_CLASS:
                /* Wa_16011157294:dg2_g10 */
@@@ -2218,12 -2300,25 +2251,25 @@@ static void blacklist_trtt(struct intel
  
  static void pvc_whitelist_build(struct intel_engine_cs *engine)
  {
-       allow_read_ctx_timestamp(engine);
- 
        /* Wa_16014440446:pvc */
        blacklist_trtt(engine);
  }
  
+ static void mtl_whitelist_build(struct intel_engine_cs *engine)
+ {
+       struct i915_wa_list *w = &engine->whitelist;
+ 
+       switch (engine->class) {
+       case RENDER_CLASS:
+               /* Required by recommended tuning setting (not a workaround) */
+               whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
+ 
+               break;
+       default:
+               break;
+       }
+ }
+ 
  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
  {
        struct drm_i915_private *i915 = engine->i915;
@@@ -2232,13 -2327,15 +2278,13 @@@
        wa_init_start(w, engine->gt, "whitelist", engine->name);
  
        if (IS_METEORLAKE(i915))
-               ; /* noop; none at this time */
+               mtl_whitelist_build(engine);
        else if (IS_PONTEVECCHIO(i915))
                pvc_whitelist_build(engine);
        else if (IS_DG2(i915))
                dg2_whitelist_build(engine);
        else if (IS_XEHPSDV(i915))
-               xehpsdv_whitelist_build(engine);
+               ; /* none needed */
 -      else if (IS_DG1(i915))
 -              dg1_whitelist_build(engine);
        else if (GRAPHICS_VER(i915) == 12)
                tgl_whitelist_build(engine);
        else if (GRAPHICS_VER(i915) == 11)
@@@ -2403,16 -2500,12 +2449,12 @@@ rcs_engine_wa_init(struct intel_engine_
                                 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
        }
  
-       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
+       if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0))
                /* Wa_22010430635:dg2 */
                wa_mcr_masked_en(wal,
                                 GEN9_ROW_CHICKEN4,
                                 GEN12_DISABLE_GRF_CLEAR);
  
-               /* Wa_14010648519:dg2 */
-               wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
-       }
- 
        /* Wa_14013202645:dg2 */
        if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
            IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
@@@ -2433,6 -2526,27 +2475,6 @@@
                           true);
        }
  
 -      if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 -          IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 -              /*
 -               * Wa_1607138336:tgl[a0],dg1[a0]
 -               * Wa_1607063988:tgl[a0],dg1[a0]
 -               */
 -              wa_write_or(wal,
 -                          GEN9_CTX_PREEMPT_REG,
 -                          GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
 -      }
 -
 -      if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
 -              /*
 -               * Wa_1606679103:tgl
 -               * (see also Wa_1606682166:icl)
 -               */
 -              wa_write_or(wal,
 -                          GEN7_SARCHKMD,
 -                          GEN7_DISABLE_SAMPLER_PREFETCH);
 -      }
 -
        if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
                /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
@@@ -2462,22 -2576,30 +2504,22 @@@
        }
  
        if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
 -          IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
            IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
 -              /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
 +              /* Wa_1409804808 */
                wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
                                 GEN12_PUSH_CONST_DEREF_HOLD_DIS);
  
 -              /*
 -               * Wa_1409085225:tgl
 -               * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
 -               */
 +              /* Wa_14010229206 */
                wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
        }
  
 -      if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
 -          IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
 +      if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
                /*
 -               * Wa_1607030317:tgl
 -               * Wa_1607186500:tgl
 -               * Wa_1607297627:tgl,rkl,dg1[a0],adlp
 +               * Wa_1607297627
                 *
                 * On TGL and RKL there are multiple entries for this WA in the
                 * BSpec; some indicate this is an A0-only WA, others indicate
                 * it applies to all steppings so we trust the "all steppings."
 -               * For DG1 this only applies to A0.
                 */
                wa_masked_en(wal,
                             RING_PSMI_CTL(RENDER_RING_BASE),
@@@ -2897,16 -3019,8 +2939,8 @@@ static voi
  add_render_compute_tuning_settings(struct drm_i915_private *i915,
                                   struct i915_wa_list *wal)
  {
-       if (IS_PONTEVECCHIO(i915)) {
-               wa_mcr_write(wal, XEHPC_L3SCRUB,
-                            SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
-               wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
-       }
- 
-       if (IS_DG2(i915)) {
-               wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+       if (IS_DG2(i915))
                wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
-       }
  
        /*
         * This tuning setting proves beneficial only on ATS-M designs; the
@@@ -2988,11 -3102,6 +3022,6 @@@ general_render_compute_wa_init(struct i
                           0, false);
        }
  
-       if (IS_PONTEVECCHIO(i915)) {
-               /* Wa_16016694945 */
-               wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
-       }
- 
        if (IS_XEHPSDV(i915)) {
                /* Wa_1409954639 */
                wa_mcr_masked_en(wal,
@@@ -3004,18 -3113,9 +3033,9 @@@
                                 GEN9_ROW_CHICKEN4,
                                 GEN12_DISABLE_GRF_CLEAR);
  
-               /* Wa_14010670810:xehpsdv */
-               wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
- 
                /* Wa_14010449647:xehpsdv */
                wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
                                 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
- 
-               /* Wa_18011725039:xehpsdv */
-               if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
-                       wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
-                       wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
-               }
        }
  
        if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {

diff --combined drivers/gpu/drm/i915/i915_driver.c
index db7a86def7e222581f6058e3b6df0aeb80e615d5,19983b77118d6bf9ad6c783f32392e6e5a5300ec..a53fd339e2cc94ec65bce55422ae8b61ac71d0cc
--- 1/drivers/gpu/drm/i915/i915_driver.c
--- 2/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@@ -34,6 -34,7 +34,6 @@@
  #include <linux/pci.h>
  #include <linux/pm.h>
  #include <linux/pm_runtime.h>
 -#include <linux/pnp.h>
  #include <linux/slab.h>
  #include <linux/string_helpers.h>
  #include <linux/vga_switcheroo.h>
@@@ -77,7 -78,6 +77,7 @@@
  #include "pxp/intel_pxp_pm.h"
  
  #include "soc/intel_dram.h"
 +#include "soc/intel_gmch.h"
  
  #include "i915_file_private.h"
  #include "i915_debugfs.h"
@@@ -107,6 -107,141 +107,6 @@@
  
  static const struct drm_driver i915_drm_driver;
  
 -static void i915_release_bridge_dev(struct drm_device *dev,
 -                                  void *bridge)
 -{
 -      pci_dev_put(bridge);
 -}
 -
 -static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 -{
 -      int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
 -
 -      dev_priv->bridge_dev =
 -              pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 -      if (!dev_priv->bridge_dev) {
 -              drm_err(&dev_priv->drm, "bridge device not found\n");
 -              return -EIO;
 -      }
 -
 -      return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
 -                                      dev_priv->bridge_dev);
 -}
 -
 -/* Allocate space for the MCH regs if needed, return nonzero on error */
 -static int
 -intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 -{
 -      int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 -      u32 temp_lo, temp_hi = 0;
 -      u64 mchbar_addr;
 -      int ret;
 -
 -      if (GRAPHICS_VER(dev_priv) >= 4)
 -              pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 -      pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 -      mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 -
 -      /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 -#ifdef CONFIG_PNP
 -      if (mchbar_addr &&
 -          pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 -              return 0;
 -#endif
 -
 -      /* Get some space for it */
 -      dev_priv->mch_res.name = "i915 MCHBAR";
 -      dev_priv->mch_res.flags = IORESOURCE_MEM;
 -      ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 -                                   &dev_priv->mch_res,
 -                                   MCHBAR_SIZE, MCHBAR_SIZE,
 -                                   PCIBIOS_MIN_MEM,
 -                                   0, pcibios_align_resource,
 -                                   dev_priv->bridge_dev);
 -      if (ret) {
 -              drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 -              dev_priv->mch_res.start = 0;
 -              return ret;
 -      }
 -
 -      if (GRAPHICS_VER(dev_priv) >= 4)
 -              pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 -                                     upper_32_bits(dev_priv->mch_res.start));
 -
 -      pci_write_config_dword(dev_priv->bridge_dev, reg,
 -                             lower_32_bits(dev_priv->mch_res.start));
 -      return 0;
 -}
 -
 -/* Setup MCHBAR if possible, return true if we should disable it again */
 -static void
 -intel_setup_mchbar(struct drm_i915_private *dev_priv)
 -{
 -      int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 -      u32 temp;
 -      bool enabled;
 -
 -      if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 -              return;
 -
 -      dev_priv->mchbar_need_disable = false;
 -
 -      if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 -              pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 -              enabled = !!(temp & DEVEN_MCHBAR_EN);
 -      } else {
 -              pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 -              enabled = temp & 1;
 -      }
 -
 -      /* If it's already enabled, don't have to do anything */
 -      if (enabled)
 -              return;
 -
 -      if (intel_alloc_mchbar_resource(dev_priv))
 -              return;
 -
 -      dev_priv->mchbar_need_disable = true;
 -
 -      /* Space is allocated or reserved, so enable it. */
 -      if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 -              pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 -                                     temp | DEVEN_MCHBAR_EN);
 -      } else {
 -              pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 -              pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 -      }
 -}
 -
 -static void
 -intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 -{
 -      int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 -
 -      if (dev_priv->mchbar_need_disable) {
 -              if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 -                      u32 deven_val;
 -
 -                      pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 -                                            &deven_val);
 -                      deven_val &= ~DEVEN_MCHBAR_EN;
 -                      pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 -                                             deven_val);
 -              } else {
 -                      u32 mchbar_val;
 -
 -                      pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 -                                            &mchbar_val);
 -                      mchbar_val &= ~1;
 -                      pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 -                                             mchbar_val);
 -              }
 -      }
 -
 -      if (dev_priv->mch_res.start)
 -              release_resource(&dev_priv->mch_res);
 -}
 -
  static int i915_workqueues_init(struct drm_i915_private *dev_priv)
  {
        /*
@@@ -167,8 -302,6 +167,8 @@@ static void intel_detect_preproduction_
        pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
        pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
        pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 +      pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 +      pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
  
        if (pre) {
                drm_err(&dev_priv->drm, "This is a pre-production stepping. "
@@@ -250,6 -383,10 +250,6 @@@ static int i915_driver_early_probe(stru
        /* This must be called before any calls to HAS_PCH_* */
        intel_detect_pch(dev_priv);
  
 -      intel_pm_setup(dev_priv);
 -      ret = intel_power_domains_init(dev_priv);
 -      if (ret < 0)
 -              goto err_gem;
        intel_irq_init(dev_priv);
        intel_init_display_hooks(dev_priv);
        intel_init_clock_gating_hooks(dev_priv);
@@@ -258,6 -395,10 +258,6 @@@
  
        return 0;
  
 -err_gem:
 -      i915_gem_cleanup_early(dev_priv);
 -      intel_gt_driver_late_release_all(dev_priv);
 -      i915_drm_clients_fini(&dev_priv->clients);
  err_rootgt:
        intel_region_ttm_device_fini(dev_priv);
  err_ttm:
@@@ -306,7 -447,7 +306,7 @@@ static int i915_driver_mmio_probe(struc
        if (i915_inject_probe_failure(dev_priv))
                return -ENODEV;
  
 -      ret = i915_get_bridge_dev(dev_priv);
 +      ret = intel_gmch_bridge_setup(dev_priv);
        if (ret < 0)
                return ret;
  
@@@ -323,7 -464,7 +323,7 @@@
        }
  
        /* Try to make sure MCHBAR is enabled before poking at it */
 -      intel_setup_mchbar(dev_priv);
 +      intel_gmch_bar_setup(dev_priv);
        intel_device_info_runtime_init(dev_priv);
  
        for_each_gt(gt, dev_priv, i) {
@@@ -338,7 -479,7 +338,7 @@@
        return 0;
  
  err_uncore:
 -      intel_teardown_mchbar(dev_priv);
 +      intel_gmch_bar_teardown(dev_priv);
  
        return ret;
  }
@@@ -349,7 -490,7 +349,7 @@@
   */
  static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
  {
 -      intel_teardown_mchbar(dev_priv);
 +      intel_gmch_bar_teardown(dev_priv);
  }
  
  /**
@@@ -483,13 -624,17 +483,17 @@@ static int i915_driver_hw_probe(struct 
        if (ret)
                goto err_ggtt;
  
-       ret = intel_memory_regions_hw_probe(dev_priv);
+       /*
+        * Make sure we probe lmem before we probe stolen-lmem. The BAR size
+        * might be different due to bar resizing.
+        */
+       ret = intel_gt_tiles_init(dev_priv);
        if (ret)
                goto err_ggtt;
  
-       ret = intel_gt_tiles_init(dev_priv);
+       ret = intel_memory_regions_hw_probe(dev_priv);
        if (ret)
-               goto err_mem_regions;
+               goto err_ggtt;
  
        ret = i915_ggtt_enable_hw(dev_priv);
        if (ret) {
@@@ -932,9 -1077,10 +936,9 @@@ static void i915_driver_lastclose(struc
  {
        struct drm_i915_private *i915 = to_i915(dev);
  
 -      intel_fbdev_restore_mode(dev);
 +      intel_fbdev_restore_mode(i915);
  
 -      if (HAS_DISPLAY(i915))
 -              vga_switcheroo_process_delayed_switch();
 +      vga_switcheroo_process_delayed_switch();
  }
  
  static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
@@@ -998,7 -1144,7 +1002,7 @@@ void i915_driver_shutdown(struct drm_i9
        intel_suspend_encoders(i915);
        intel_shutdown_encoders(i915);
  
 -      intel_dmc_ucode_suspend(i915);
 +      intel_dmc_suspend(i915);
  
        i915_gem_suspend(i915);
  
@@@ -1028,13 -1174,6 +1032,13 @@@ static bool suspend_to_idle(struct drm_
        return false;
  }
  
 +static void i915_drm_complete(struct drm_device *dev)
 +{
 +      struct drm_i915_private *i915 = to_i915(dev);
 +
 +      intel_pxp_resume_complete(i915->pxp);
 +}
 +
  static int i915_drm_prepare(struct drm_device *dev)
  {
        struct drm_i915_private *i915 = to_i915(dev);
@@@ -1075,6 -1214,8 +1079,6 @@@ static int i915_drm_suspend(struct drm_
  
        intel_suspend_encoders(dev_priv);
  
 -      intel_suspend_hw(dev_priv);
 -
        /* Must be called before GGTT is suspended. */
        intel_dpt_suspend(dev_priv);
        i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
@@@ -1088,7 -1229,7 +1092,7 @@@
  
        dev_priv->suspend_count++;
  
 -      intel_dmc_ucode_suspend(dev_priv);
 +      intel_dmc_suspend(dev_priv);
  
        enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
  
@@@ -1209,7 -1350,7 +1213,7 @@@ static int i915_drm_resume(struct drm_d
        /* Must be called after GGTT is resumed. */
        intel_dpt_resume(dev_priv);
  
 -      intel_dmc_ucode_resume(dev_priv);
 +      intel_dmc_resume(dev_priv);
  
        i915_restore_display(dev_priv);
        intel_pps_unlock_regs_wa(dev_priv);
@@@ -1233,6 -1374,8 +1237,6 @@@
  
        i915_gem_resume(dev_priv);
  
 -      intel_pxp_resume(dev_priv->pxp);
 -
        intel_modeset_init_hw(dev_priv);
        intel_init_clock_gating(dev_priv);
        intel_hpd_init(dev_priv);
@@@ -1424,16 -1567,6 +1428,16 @@@ static int i915_pm_resume(struct devic
        return i915_drm_resume(&i915->drm);
  }
  
 +static void i915_pm_complete(struct device *kdev)
 +{
 +      struct drm_i915_private *i915 = kdev_to_i915(kdev);
 +
 +      if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
 +              return;
 +
 +      i915_drm_complete(&i915->drm);
 +}
 +
  /* freeze: before creating the hibernation_image */
  static int i915_pm_freeze(struct device *kdev)
  {
@@@ -1654,7 -1787,6 +1658,7 @@@ const struct dev_pm_ops i915_pm_ops = 
        .suspend_late = i915_pm_suspend_late,
        .resume_early = i915_pm_resume_early,
        .resume = i915_pm_resume,
 +      .complete = i915_pm_complete,
  
        /*
         * S4 event handlers

diff --combined drivers/gpu/drm/i915/i915_reg.h
index 1757fb8fdf5bdc71163c03bc90ca5bdf1347b3ae,cf80500fff79857edd8878ab7138ed2be22a10e9..34b7d2ac33fb0c6e7a135568882ddda181bf3852
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -116,9 -116,6 +116,9 @@@
   *  #define GEN8_BAR                    _MMIO(0xb888)
   */
  
 +#define GU_CNTL_PROTECTED             _MMIO(0x10100C)
 +#define   DEPRESENT                   REG_BIT(9)
 +
  #define GU_CNTL                               _MMIO(0x101010)
  #define   LMEM_INIT                   REG_BIT(7)
  #define   DRIVERFLR                   REG_BIT(31)
@@@ -544,10 -541,9 +544,10 @@@
  #define _BXT_PHY0_BASE                        0x6C000
  #define _BXT_PHY1_BASE                        0x162000
  #define _BXT_PHY2_BASE                        0x163000
 -#define BXT_PHY_BASE(phy)             _PHY3((phy), _BXT_PHY0_BASE, \
 -                                                   _BXT_PHY1_BASE, \
 -                                                   _BXT_PHY2_BASE)
 +#define BXT_PHY_BASE(phy)                                                     \
 +       _PICK_EVEN_2RANGES(phy, 1,                                             \
 +                          _BXT_PHY0_BASE, _BXT_PHY0_BASE,                     \
 +                          _BXT_PHY1_BASE, _BXT_PHY2_BASE)
  
  #define _BXT_PHY(phy, reg)                                            \
        _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
@@@ -570,14 -566,13 +570,14 @@@
  #define BXT_PHY_CTL(port)             _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
                                                         _BXT_PHY_CTL_DDI_B)
  
 -#define _PHY_CTL_FAMILY_EDP           0x64C80
  #define _PHY_CTL_FAMILY_DDI           0x64C90
 +#define _PHY_CTL_FAMILY_EDP           0x64C80
  #define _PHY_CTL_FAMILY_DDI_C         0x64CA0
  #define   COMMON_RESET_DIS            (1 << 31)
 -#define BXT_PHY_CTL_FAMILY(phy)               _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
 -                                                        _PHY_CTL_FAMILY_EDP, \
 -                                                        _PHY_CTL_FAMILY_DDI_C)
 +#define BXT_PHY_CTL_FAMILY(phy)                                                       \
 +       _MMIO(_PICK_EVEN_2RANGES(phy, 1,                                       \
 +                                _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI,     \
 +                                _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
  
  /* BXT PHY PLL registers */
  #define _PORT_PLL_A                   0x46074
@@@ -1043,11 -1038,9 +1043,11 @@@
  #define _MBUS_ABOX0_CTL                       0x45038
  #define _MBUS_ABOX1_CTL                       0x45048
  #define _MBUS_ABOX2_CTL                       0x4504C
 -#define MBUS_ABOX_CTL(x)              _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \
 -                                                  _MBUS_ABOX1_CTL, \
 -                                                  _MBUS_ABOX2_CTL))
 +#define MBUS_ABOX_CTL(x)                                                      \
 +      _MMIO(_PICK_EVEN_2RANGES(x, 2,                                          \
 +                               _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL,              \
 +                               _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
 +
  #define MBUS_ABOX_BW_CREDIT_MASK      (3 << 20)
  #define MBUS_ABOX_BW_CREDIT(x)                ((x) << 20)
  #define MBUS_ABOX_B_CREDIT_MASK               (0xF << 16)
@@@ -1737,11 -1730,10 +1737,11 @@@
  #define   PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
  #define   PALETTE_10BIT_BLUE_MANT_MASK        REG_GENMASK(5, 2)
  #define   PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
 -#define PALETTE(pipe, i)      _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
 -                                    _PICK((pipe), _PALETTE_A,         \
 -                                          _PALETTE_B, _CHV_PALETTE_C) + \
 -                                    (i) * 4)
 +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +                  \
 +                             _PICK_EVEN_2RANGES(pipe, 2,                      \
 +                                                _PALETTE_A, _PALETTE_B,       \
 +                                                _CHV_PALETTE_C, _CHV_PALETTE_C) + \
 +                                                (i) * 4)
  
  #define PEG_BAND_GAP_DATA     _MMIO(0x14d68)
  
@@@ -1914,72 -1906,48 +1914,72 @@@
  #define PIPE_CRC_RES_RES1_I915(pipe)  _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
  #define PIPE_CRC_RES_RES2_G4X(pipe)   _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
  
 -/* Pipe A timing regs */
 -#define _HTOTAL_A     0x60000
 -#define _HBLANK_A     0x60004
 -#define _HSYNC_A      0x60008
 -#define _VTOTAL_A     0x6000c
 -#define _VBLANK_A     0x60010
 -#define _VSYNC_A      0x60014
 -#define _EXITLINE_A   0x60018
 -#define _PIPEASRC     0x6001c
 +/* Pipe/transcoder A timing regs */
 +#define _TRANS_HTOTAL_A               0x60000
 +#define   HTOTAL_MASK                 REG_GENMASK(31, 16)
 +#define   HTOTAL(htotal)              REG_FIELD_PREP(HTOTAL_MASK, (htotal))
 +#define   HACTIVE_MASK                        REG_GENMASK(15, 0)
 +#define   HACTIVE(hdisplay)           REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
 +#define _TRANS_HBLANK_A               0x60004
 +#define   HBLANK_END_MASK             REG_GENMASK(31, 16)
 +#define   HBLANK_END(hblank_end)      REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
 +#define   HBLANK_START_MASK           REG_GENMASK(15, 0)
 +#define   HBLANK_START(hblank_start)  REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
 +#define _TRANS_HSYNC_A                0x60008
 +#define   HSYNC_END_MASK              REG_GENMASK(31, 16)
 +#define   HSYNC_END(hsync_end)                REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
 +#define   HSYNC_START_MASK            REG_GENMASK(15, 0)
 +#define   HSYNC_START(hsync_start)    REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
 +#define _TRANS_VTOTAL_A               0x6000c
 +#define   VTOTAL_MASK                 REG_GENMASK(31, 16)
 +#define   VTOTAL(vtotal)              REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
 +#define   VACTIVE_MASK                        REG_GENMASK(15, 0)
 +#define   VACTIVE(vdisplay)           REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
 +#define _TRANS_VBLANK_A               0x60010
 +#define   VBLANK_END_MASK             REG_GENMASK(31, 16)
 +#define   VBLANK_END(vblank_end)      REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
 +#define   VBLANK_START_MASK           REG_GENMASK(15, 0)
 +#define   VBLANK_START(vblank_start)  REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
 +#define _TRANS_VSYNC_A                0x60014
 +#define   VSYNC_END_MASK              REG_GENMASK(31, 16)
 +#define   VSYNC_END(vsync_end)                REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
 +#define   VSYNC_START_MASK            REG_GENMASK(15, 0)
 +#define   VSYNC_START(vsync_start)    REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
 +#define _TRANS_EXITLINE_A     0x60018
 +#define _PIPEASRC             0x6001c
  #define   PIPESRC_WIDTH_MASK  REG_GENMASK(31, 16)
  #define   PIPESRC_WIDTH(w)    REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
  #define   PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
  #define   PIPESRC_HEIGHT(h)   REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
 -#define _BCLRPAT_A    0x60020
 -#define _VSYNCSHIFT_A 0x60028
 -#define _PIPE_MULT_A  0x6002c
 -
 -/* Pipe B timing regs */
 -#define _HTOTAL_B     0x61000
 -#define _HBLANK_B     0x61004
 -#define _HSYNC_B      0x61008
 -#define _VTOTAL_B     0x6100c
 -#define _VBLANK_B     0x61010
 -#define _VSYNC_B      0x61014
 -#define _PIPEBSRC     0x6101c
 -#define _BCLRPAT_B    0x61020
 -#define _VSYNCSHIFT_B 0x61028
 -#define _PIPE_MULT_B  0x6102c
 +#define _BCLRPAT_A            0x60020
 +#define _TRANS_VSYNCSHIFT_A   0x60028
 +#define _TRANS_MULT_A         0x6002c
 +
 +/* Pipe/transcoder B timing regs */
 +#define _TRANS_HTOTAL_B               0x61000
 +#define _TRANS_HBLANK_B               0x61004
 +#define _TRANS_HSYNC_B                0x61008
 +#define _TRANS_VTOTAL_B               0x6100c
 +#define _TRANS_VBLANK_B               0x61010
 +#define _TRANS_VSYNC_B                0x61014
 +#define _PIPEBSRC             0x6101c
 +#define _BCLRPAT_B            0x61020
 +#define _TRANS_VSYNCSHIFT_B   0x61028
 +#define _TRANS_MULT_B         0x6102c
  
  /* DSI 0 timing regs */
 -#define _HTOTAL_DSI0          0x6b000
 -#define _HSYNC_DSI0           0x6b008
 -#define _VTOTAL_DSI0          0x6b00c
 -#define _VSYNC_DSI0           0x6b014
 -#define _VSYNCSHIFT_DSI0      0x6b028
 +#define _TRANS_HTOTAL_DSI0    0x6b000
 +#define _TRANS_HSYNC_DSI0     0x6b008
 +#define _TRANS_VTOTAL_DSI0    0x6b00c
 +#define _TRANS_VSYNC_DSI0     0x6b014
 +#define _TRANS_VSYNCSHIFT_DSI0        0x6b028
  
  /* DSI 1 timing regs */
 -#define _HTOTAL_DSI1          0x6b800
 -#define _HSYNC_DSI1           0x6b808
 -#define _VTOTAL_DSI1          0x6b80c
 -#define _VSYNC_DSI1           0x6b814
 -#define _VSYNCSHIFT_DSI1      0x6b828
 +#define _TRANS_HTOTAL_DSI1    0x6b800
 +#define _TRANS_HSYNC_DSI1     0x6b808
 +#define _TRANS_VTOTAL_DSI1    0x6b80c
 +#define _TRANS_VSYNC_DSI1     0x6b814
 +#define _TRANS_VSYNCSHIFT_DSI1        0x6b828
  
  #define TRANSCODER_A_OFFSET 0x60000
  #define TRANSCODER_B_OFFSET 0x61000
@@@ -1990,18 -1958,18 +1990,18 @@@
  #define TRANSCODER_DSI0_OFFSET        0x6b000
  #define TRANSCODER_DSI1_OFFSET        0x6b800
  
 -#define HTOTAL(trans)         _MMIO_TRANS2(trans, _HTOTAL_A)
 -#define HBLANK(trans)         _MMIO_TRANS2(trans, _HBLANK_A)
 -#define HSYNC(trans)          _MMIO_TRANS2(trans, _HSYNC_A)
 -#define VTOTAL(trans)         _MMIO_TRANS2(trans, _VTOTAL_A)
 -#define VBLANK(trans)         _MMIO_TRANS2(trans, _VBLANK_A)
 -#define VSYNC(trans)          _MMIO_TRANS2(trans, _VSYNC_A)
 -#define BCLRPAT(trans)                _MMIO_TRANS2(trans, _BCLRPAT_A)
 -#define VSYNCSHIFT(trans)     _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 -#define PIPESRC(trans)                _MMIO_TRANS2(trans, _PIPEASRC)
 -#define PIPE_MULT(trans)      _MMIO_TRANS2(trans, _PIPE_MULT_A)
 -
 -#define EXITLINE(trans)               _MMIO_TRANS2(trans, _EXITLINE_A)
 +#define TRANS_HTOTAL(trans)   _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
 +#define TRANS_HBLANK(trans)   _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
 +#define TRANS_HSYNC(trans)    _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
 +#define TRANS_VTOTAL(trans)   _MMIO_TRANS2((trans), _TRANS_VTOTAL_A)
 +#define TRANS_VBLANK(trans)   _MMIO_TRANS2((trans), _TRANS_VBLANK_A)
 +#define TRANS_VSYNC(trans)    _MMIO_TRANS2((trans), _TRANS_VSYNC_A)
 +#define BCLRPAT(trans)                _MMIO_TRANS2((trans), _BCLRPAT_A)
 +#define TRANS_VSYNCSHIFT(trans)       _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A)
 +#define PIPESRC(pipe)         _MMIO_TRANS2((pipe), _PIPEASRC)
 +#define TRANS_MULT(trans)     _MMIO_TRANS2((trans), _TRANS_MULT_A)
 +
 +#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A)
  #define   EXITLINE_ENABLE     REG_BIT(31)
  #define   EXITLINE_MASK               REG_GENMASK(12, 0)
  #define   EXITLINE_SHIFT      0
@@@ -2298,6 -2266,110 +2298,6 @@@
  #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME           REG_BIT(14)
  #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME                REG_BIT(13)
  
 -/* Icelake DSC Rate Control Range Parameter Registers */
 -#define DSCA_RC_RANGE_PARAMETERS_0            _MMIO(0x6B240)
 -#define DSCA_RC_RANGE_PARAMETERS_0_UDW                _MMIO(0x6B240 + 4)
 -#define DSCC_RC_RANGE_PARAMETERS_0            _MMIO(0x6BA40)
 -#define DSCC_RC_RANGE_PARAMETERS_0_UDW                _MMIO(0x6BA40 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB    (0x78208)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB        (0x78208 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB    (0x78308)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB        (0x78308 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC    (0x78408)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC        (0x78408 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC    (0x78508)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC        (0x78508 + 4)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
 -#define RC_BPG_OFFSET_SHIFT                   10
 -#define RC_MAX_QP_SHIFT                               5
 -#define RC_MIN_QP_SHIFT                               0
 -
 -#define DSCA_RC_RANGE_PARAMETERS_1            _MMIO(0x6B248)
 -#define DSCA_RC_RANGE_PARAMETERS_1_UDW                _MMIO(0x6B248 + 4)
 -#define DSCC_RC_RANGE_PARAMETERS_1            _MMIO(0x6BA48)
 -#define DSCC_RC_RANGE_PARAMETERS_1_UDW                _MMIO(0x6BA48 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB    (0x78210)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB        (0x78210 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB    (0x78310)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB        (0x78310 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC    (0x78410)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC        (0x78410 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC    (0x78510)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC        (0x78510 + 4)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
 -
 -#define DSCA_RC_RANGE_PARAMETERS_2            _MMIO(0x6B250)
 -#define DSCA_RC_RANGE_PARAMETERS_2_UDW                _MMIO(0x6B250 + 4)
 -#define DSCC_RC_RANGE_PARAMETERS_2            _MMIO(0x6BA50)
 -#define DSCC_RC_RANGE_PARAMETERS_2_UDW                _MMIO(0x6BA50 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB    (0x78218)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB        (0x78218 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB    (0x78318)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB        (0x78318 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC    (0x78418)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC        (0x78418 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC    (0x78518)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC        (0x78518 + 4)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
 -
 -#define DSCA_RC_RANGE_PARAMETERS_3            _MMIO(0x6B258)
 -#define DSCA_RC_RANGE_PARAMETERS_3_UDW                _MMIO(0x6B258 + 4)
 -#define DSCC_RC_RANGE_PARAMETERS_3            _MMIO(0x6BA58)
 -#define DSCC_RC_RANGE_PARAMETERS_3_UDW                _MMIO(0x6BA58 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB    (0x78220)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB        (0x78220 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB    (0x78320)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB        (0x78320 + 4)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC    (0x78420)
 -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC        (0x78420 + 4)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC    (0x78520)
 -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC        (0x78520 + 4)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
 -#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
 -                                                      _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)          _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
 -#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)      _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
 -                                                      _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
 -
  /* VGA port control */
  #define ADPA                  _MMIO(0x61100)
  #define PCH_ADPA                _MMIO(0xe1100)
@@@ -2379,7 -2451,18 +2379,7 @@@
  #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV      (1 << 2)
  
  #define PORT_HOTPLUG_STAT     _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
 -/*
 - * HDMI/DP bits are g4x+
 - *
 - * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
 - * Please check the detailed lore in the commit message for for experimental
 - * evidence.
 - */
 -/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
 -#define   PORTD_HOTPLUG_LIVE_STATUS_GM45      (1 << 29)
 -#define   PORTC_HOTPLUG_LIVE_STATUS_GM45      (1 << 28)
 -#define   PORTB_HOTPLUG_LIVE_STATUS_GM45      (1 << 27)
 -/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
 +/* HDMI/DP bits are g4x+ */
  #define   PORTD_HOTPLUG_LIVE_STATUS_G4X               (1 << 27)
  #define   PORTC_HOTPLUG_LIVE_STATUS_G4X               (1 << 28)
  #define   PORTB_HOTPLUG_LIVE_STATUS_G4X               (1 << 29)
@@@ -2509,6 -2592,59 +2509,6 @@@
  #define   SDVO_PIPE_SEL_MASK_CHV              (3 << 24)
  #define   SDVO_PIPE_SEL_CHV(pipe)             ((pipe) << 24)
  
 -/* LVDS port control */
 -#define LVDS                  _MMIO(0x61180)
 -/*
 - * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
 - * the DPLL semantics change when the LVDS is assigned to that pipe.
 - */
 -#define   LVDS_PORT_EN                        (1 << 31)
 -/* Selects pipe B for LVDS data.  Must be set on pre-965. */
 -#define   LVDS_PIPE_SEL_SHIFT         30
 -#define   LVDS_PIPE_SEL_MASK          (1 << 30)
 -#define   LVDS_PIPE_SEL(pipe)         ((pipe) << 30)
 -#define   LVDS_PIPE_SEL_SHIFT_CPT     29
 -#define   LVDS_PIPE_SEL_MASK_CPT      (3 << 29)
 -#define   LVDS_PIPE_SEL_CPT(pipe)     ((pipe) << 29)
 -/* LVDS dithering flag on 965/g4x platform */
 -#define   LVDS_ENABLE_DITHER          (1 << 25)
 -/* LVDS sync polarity flags. Set to invert (i.e. negative) */
 -#define   LVDS_VSYNC_POLARITY         (1 << 21)
 -#define   LVDS_HSYNC_POLARITY         (1 << 20)
 -
 -/* Enable border for unscaled (or aspect-scaled) display */
 -#define   LVDS_BORDER_ENABLE          (1 << 15)
 -/*
 - * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
 - * pixel.
 - */
 -#define   LVDS_A0A2_CLKA_POWER_MASK   (3 << 8)
 -#define   LVDS_A0A2_CLKA_POWER_DOWN   (0 << 8)
 -#define   LVDS_A0A2_CLKA_POWER_UP     (3 << 8)
 -/*
 - * Controls the A3 data pair, which contains the additional LSBs for 24 bit
 - * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
 - * on.
 - */
 -#define   LVDS_A3_POWER_MASK          (3 << 6)
 -#define   LVDS_A3_POWER_DOWN          (0 << 6)
 -#define   LVDS_A3_POWER_UP            (3 << 6)
 -/*
 - * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
 - * is set.
 - */
 -#define   LVDS_CLKB_POWER_MASK                (3 << 4)
 -#define   LVDS_CLKB_POWER_DOWN                (0 << 4)
 -#define   LVDS_CLKB_POWER_UP          (3 << 4)
 -/*
 - * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
 - * setting for whether we are in dual-channel mode.  The B3 pair will
 - * additionally only be powered up when LVDS_A3_POWER_UP is set.
 - */
 -#define   LVDS_B0B3_POWER_MASK                (3 << 2)
 -#define   LVDS_B0B3_POWER_DOWN                (0 << 2)
 -#define   LVDS_B0B3_POWER_UP          (3 << 2)
 -
  /* Video Data Island Packet control */
  #define VIDEO_DIP_DATA                _MMIO(0x61178)
  /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
@@@ -3356,61 -3492,61 +3356,61 @@@
  #define _PIPEADSL             0x70000
  #define   PIPEDSL_CURR_FIELD  REG_BIT(31) /* ctg+ */
  #define   PIPEDSL_LINE_MASK   REG_GENMASK(19, 0)
 -#define _PIPEACONF            0x70008
 -#define   PIPECONF_ENABLE                     REG_BIT(31)
 -#define   PIPECONF_DOUBLE_WIDE                        REG_BIT(30) /* pre-i965 */
 -#define   PIPECONF_STATE_ENABLE                       REG_BIT(30) /* i965+ */
 -#define   PIPECONF_DSI_PLL_LOCKED             REG_BIT(29) /* vlv & pipe A only */
 -#define   PIPECONF_FRAME_START_DELAY_MASK     REG_GENMASK(28, 27) /* pre-hsw */
 -#define   PIPECONF_FRAME_START_DELAY(x)               REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
 -#define   PIPECONF_PIPE_LOCKED                        REG_BIT(25)
 -#define   PIPECONF_FORCE_BORDER                       REG_BIT(25)
 -#define   PIPECONF_GAMMA_MODE_MASK_I9XX               REG_BIT(24) /* gmch */
 -#define   PIPECONF_GAMMA_MODE_MASK_ILK                REG_GENMASK(25, 24) /* ilk-ivb */
 -#define   PIPECONF_GAMMA_MODE_8BIT            REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
 -#define   PIPECONF_GAMMA_MODE_10BIT           REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
 -#define   PIPECONF_GAMMA_MODE_12BIT           REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
 -#define   PIPECONF_GAMMA_MODE_SPLIT           REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
 -#define   PIPECONF_GAMMA_MODE(x)              REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
 -#define   PIPECONF_INTERLACE_MASK             REG_GENMASK(23, 21) /* gen3+ */
 -#define   PIPECONF_INTERLACE_PROGRESSIVE      REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
 -#define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL       REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
 -#define   PIPECONF_INTERLACE_W_SYNC_SHIFT     REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
 -#define   PIPECONF_INTERLACE_W_FIELD_INDICATION       REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
 -#define   PIPECONF_INTERLACE_FIELD_0_ONLY     REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
 +#define _TRANSACONF           0x70008
 +#define   TRANSCONF_ENABLE                    REG_BIT(31)
 +#define   TRANSCONF_DOUBLE_WIDE                       REG_BIT(30) /* pre-i965 */
 +#define   TRANSCONF_STATE_ENABLE                      REG_BIT(30) /* i965+ */
 +#define   TRANSCONF_DSI_PLL_LOCKED            REG_BIT(29) /* vlv & pipe A only */
 +#define   TRANSCONF_FRAME_START_DELAY_MASK    REG_GENMASK(28, 27) /* pre-hsw */
 +#define   TRANSCONF_FRAME_START_DELAY(x)              REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
 +#define   TRANSCONF_PIPE_LOCKED                       REG_BIT(25)
 +#define   TRANSCONF_FORCE_BORDER                      REG_BIT(25)
 +#define   TRANSCONF_GAMMA_MODE_MASK_I9XX              REG_BIT(24) /* gmch */
 +#define   TRANSCONF_GAMMA_MODE_MASK_ILK               REG_GENMASK(25, 24) /* ilk-ivb */
 +#define   TRANSCONF_GAMMA_MODE_8BIT           REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
 +#define   TRANSCONF_GAMMA_MODE_10BIT          REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
 +#define   TRANSCONF_GAMMA_MODE_12BIT          REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
 +#define   TRANSCONF_GAMMA_MODE_SPLIT          REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
 +#define   TRANSCONF_GAMMA_MODE(x)             REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
 +#define   TRANSCONF_INTERLACE_MASK            REG_GENMASK(23, 21) /* gen3+ */
 +#define   TRANSCONF_INTERLACE_PROGRESSIVE     REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
 +#define   TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL      REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
 +#define   TRANSCONF_INTERLACE_W_SYNC_SHIFT    REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
 +#define   TRANSCONF_INTERLACE_W_FIELD_INDICATION      REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
 +#define   TRANSCONF_INTERLACE_FIELD_0_ONLY    REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
  /*
   * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
   * DBL=power saving pixel doubling, PF-ID* requires panel fitter
   */
 -#define   PIPECONF_INTERLACE_MASK_ILK         REG_GENMASK(23, 21) /* ilk+ */
 -#define   PIPECONF_INTERLACE_MASK_HSW         REG_GENMASK(22, 21) /* hsw+ */
 -#define   PIPECONF_INTERLACE_PF_PD_ILK                REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
 -#define   PIPECONF_INTERLACE_PF_ID_ILK                REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
 -#define   PIPECONF_INTERLACE_IF_ID_ILK                REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
 -#define   PIPECONF_INTERLACE_IF_ID_DBL_ILK    REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
 -#define   PIPECONF_INTERLACE_PF_ID_DBL_ILK    REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
 -#define   PIPECONF_REFRESH_RATE_ALT_ILK               REG_BIT(20)
 -#define   PIPECONF_MSA_TIMING_DELAY_MASK      REG_GENMASK(19, 18) /* ilk/snb/ivb */
 -#define   PIPECONF_MSA_TIMING_DELAY(x)                REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
 -#define   PIPECONF_CXSR_DOWNCLOCK             REG_BIT(16)
 -#define   PIPECONF_REFRESH_RATE_ALT_VLV               REG_BIT(14)
 -#define   PIPECONF_COLOR_RANGE_SELECT         REG_BIT(13)
 -#define   PIPECONF_OUTPUT_COLORSPACE_MASK     REG_GENMASK(12, 11) /* ilk-ivb */
 -#define   PIPECONF_OUTPUT_COLORSPACE_RGB      REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
 -#define   PIPECONF_OUTPUT_COLORSPACE_YUV601   REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
 -#define   PIPECONF_OUTPUT_COLORSPACE_YUV709   REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
 -#define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW  REG_BIT(11) /* hsw only */
 -#define   PIPECONF_BPC_MASK                   REG_GENMASK(7, 5) /* ctg-ivb */
 -#define   PIPECONF_BPC_8                      REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
 -#define   PIPECONF_BPC_10                     REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
 -#define   PIPECONF_BPC_6                      REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
 -#define   PIPECONF_BPC_12                     REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
 -#define   PIPECONF_DITHER_EN                  REG_BIT(4)
 -#define   PIPECONF_DITHER_TYPE_MASK           REG_GENMASK(3, 2)
 -#define   PIPECONF_DITHER_TYPE_SP             REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
 -#define   PIPECONF_DITHER_TYPE_ST1            REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
 -#define   PIPECONF_DITHER_TYPE_ST2            REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
 -#define   PIPECONF_DITHER_TYPE_TEMP           REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
 +#define   TRANSCONF_INTERLACE_MASK_ILK                REG_GENMASK(23, 21) /* ilk+ */
 +#define   TRANSCONF_INTERLACE_MASK_HSW                REG_GENMASK(22, 21) /* hsw+ */
 +#define   TRANSCONF_INTERLACE_PF_PD_ILK               REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
 +#define   TRANSCONF_INTERLACE_PF_ID_ILK               REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
 +#define   TRANSCONF_INTERLACE_IF_ID_ILK               REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
 +#define   TRANSCONF_INTERLACE_IF_ID_DBL_ILK   REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
 +#define   TRANSCONF_INTERLACE_PF_ID_DBL_ILK   REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
 +#define   TRANSCONF_REFRESH_RATE_ALT_ILK              REG_BIT(20)
 +#define   TRANSCONF_MSA_TIMING_DELAY_MASK     REG_GENMASK(19, 18) /* ilk/snb/ivb */
 +#define   TRANSCONF_MSA_TIMING_DELAY(x)               REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
 +#define   TRANSCONF_CXSR_DOWNCLOCK            REG_BIT(16)
 +#define   TRANSCONF_REFRESH_RATE_ALT_VLV              REG_BIT(14)
 +#define   TRANSCONF_COLOR_RANGE_SELECT                REG_BIT(13)
 +#define   TRANSCONF_OUTPUT_COLORSPACE_MASK    REG_GENMASK(12, 11) /* ilk-ivb */
 +#define   TRANSCONF_OUTPUT_COLORSPACE_RGB     REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
 +#define   TRANSCONF_OUTPUT_COLORSPACE_YUV601  REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
 +#define   TRANSCONF_OUTPUT_COLORSPACE_YUV709  REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
 +#define   TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
 +#define   TRANSCONF_BPC_MASK                  REG_GENMASK(7, 5) /* ctg-ivb */
 +#define   TRANSCONF_BPC_8                     REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
 +#define   TRANSCONF_BPC_10                    REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
 +#define   TRANSCONF_BPC_6                     REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
 +#define   TRANSCONF_BPC_12                    REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
 +#define   TRANSCONF_DITHER_EN                 REG_BIT(4)
 +#define   TRANSCONF_DITHER_TYPE_MASK          REG_GENMASK(3, 2)
 +#define   TRANSCONF_DITHER_TYPE_SP            REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
 +#define   TRANSCONF_DITHER_TYPE_ST1           REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
 +#define   TRANSCONF_DITHER_TYPE_ST2           REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
 +#define   TRANSCONF_DITHER_TYPE_TEMP          REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
  #define _PIPEASTAT            0x70024
  #define   PIPE_FIFO_UNDERRUN_STATUS           (1UL << 31)
  #define   SPRITE1_FLIP_DONE_INT_EN_VLV                (1UL << 30)
@@@ -3479,7 -3615,7 +3479,7 @@@
  #define PIPE_DSI0_OFFSET      0x7b000
  #define PIPE_DSI1_OFFSET      0x7b800
  
 -#define PIPECONF(pipe)                _MMIO_PIPE2(pipe, _PIPEACONF)
 +#define TRANSCONF(trans)      _MMIO_PIPE2((trans), _TRANSACONF)
  #define PIPEDSL(pipe)         _MMIO_PIPE2(pipe, _PIPEADSL)
  #define PIPEFRAME(pipe)               _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
  #define PIPEFRAMEPIXEL(pipe)  _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
@@@ -4119,7 -4255,7 +4119,7 @@@
  
  /* Pipe B */
  #define _PIPEBDSL             (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
 -#define _PIPEBCONF            (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
 +#define _TRANSBCONF           (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
  #define _PIPEBSTAT            (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
  #define _PIPEBFRAMEHIGH               0x71040
  #define _PIPEBFRAMEPIXEL      0x71044
@@@ -5296,7 -5432,6 +5296,7 @@@
  #define  GEN8_PIPE_CDCLK_CRC_DONE     (1 << 28)
  #define  XELPD_PIPE_SOFT_UNDERRUN     (1 << 22)
  #define  XELPD_PIPE_HARD_UNDERRUN     (1 << 21)
 +#define  GEN12_PIPE_VBLANK_UNMOD      (1 << 19)
  #define  GEN8_PIPE_CURSOR_FAULT               (1 << 10)
  #define  GEN8_PIPE_SPRITE_FAULT               (1 << 9)
  #define  GEN8_PIPE_PRIMARY_FAULT      (1 << 8)
@@@ -5602,7 -5737,6 +5602,7 @@@
  #define  RESET_PCH_HANDSHAKE_ENABLE   REG_BIT(4)
  
  #define GEN8_CHICKEN_DCPR_1                   _MMIO(0x46430)
 +#define   LATENCY_REPORTING_REMOVED_PIPE_D    REG_BIT(31)
  #define   SKL_SELECT_ALTERNATE_DC_EXIT                REG_BIT(30)
  #define   LATENCY_REPORTING_REMOVED_PIPE_C    REG_BIT(25)
  #define   LATENCY_REPORTING_REMOVED_PIPE_B    REG_BIT(24)
@@@ -6257,6 -6391,9 +6257,6 @@@
  #define FDI_PLL_CTL_1           _MMIO(0xfe000)
  #define FDI_PLL_CTL_2           _MMIO(0xfe004)
  
 -#define PCH_LVDS      _MMIO(0xe1180)
 -#define  LVDS_DETECTED        (1 << 1)
 -
  #define _PCH_DP_B             0xe4100
  #define PCH_DP_B              _MMIO(_PCH_DP_B)
  #define _PCH_DPB_AUX_CH_CTL   0xe4110
@@@ -6458,15 -6595,6 +6458,6 @@@
  /*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
  #define     PCODE_MBOX_DOMAIN_NONE            0x0
  #define     PCODE_MBOX_DOMAIN_MEDIAFF         0x3
- 
- /* Wa_14017210380: mtl */
- #define   PCODE_MBOX_GT_STATE                 0x50
- /* sub-commands (param1) */
- #define     PCODE_MBOX_GT_STATE_MEDIA_BUSY    0x1
- #define     PCODE_MBOX_GT_STATE_MEDIA_NOT_BUSY        0x2
- /* param2 */
- #define     PCODE_MBOX_GT_STATE_DOMAIN_MEDIA  0x1
- 
  #define GEN6_PCODE_DATA                               _MMIO(0x138128)
  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT      8
  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT    16
@@@ -7086,23 -7214,21 +7077,23 @@@ enum skl_power_gate 
                                                        ADLS_DPCLKA_DDIK_SEL_MASK)
  
  /* ICL PLL */
 -#define DPLL0_ENABLE          0x46010
 -#define DPLL1_ENABLE          0x46014
 +#define _DPLL0_ENABLE         0x46010
 +#define _DPLL1_ENABLE         0x46014
  #define _ADLS_DPLL2_ENABLE    0x46018
  #define _ADLS_DPLL3_ENABLE    0x46030
 -#define  PLL_ENABLE           (1 << 31)
 -#define  PLL_LOCK             (1 << 30)
 -#define  PLL_POWER_ENABLE     (1 << 27)
 -#define  PLL_POWER_STATE      (1 << 26)
 -#define ICL_DPLL_ENABLE(pll)  _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
 -                                         _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
 +#define   PLL_ENABLE          REG_BIT(31)
 +#define   PLL_LOCK            REG_BIT(30)
 +#define   PLL_POWER_ENABLE    REG_BIT(27)
 +#define   PLL_POWER_STATE     REG_BIT(26)
 +#define ICL_DPLL_ENABLE(pll)  _MMIO(_PICK_EVEN_2RANGES(pll, 3,                        \
 +                                                      _DPLL0_ENABLE, _DPLL1_ENABLE,   \
 +                                                      _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
  
  #define _DG2_PLL3_ENABLE      0x4601C
  
 -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
 -                                     _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
 +#define DG2_PLL_ENABLE(pll)   _MMIO(_PICK_EVEN_2RANGES(pll, 3,                        \
 +                                                      _DPLL0_ENABLE, _DPLL1_ENABLE,   \
 +                                                      _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
  
  #define TBT_PLL_ENABLE                _MMIO(0x46020)
  
@@@ -7110,14 -7236,13 +7101,14 @@@
  #define _MG_PLL2_ENABLE               0x46034
  #define _MG_PLL3_ENABLE               0x46038
  #define _MG_PLL4_ENABLE               0x4603C
 -/* Bits are the same as DPLL0_ENABLE */
 +/* Bits are the same as _DPLL0_ENABLE */
  #define MG_PLL_ENABLE(tc_port)        _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
                                           _MG_PLL2_ENABLE)
  
  /* DG1 PLL */
 -#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
 -                                         _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
 +#define DG1_DPLL_ENABLE(pll)    _MMIO(_PICK_EVEN_2RANGES(pll, 2,                      \
 +                                                      _DPLL0_ENABLE, _DPLL1_ENABLE,   \
 +                                                      _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
  
  /* ADL-P Type C PLL */
  #define PORTTC1_PLL_ENABLE    0x46038
@@@ -7177,9 -7302,9 +7168,9 @@@
  #define _TGL_DPLL0_CFGCR0             0x164284
  #define _TGL_DPLL1_CFGCR0             0x16428C
  #define _TGL_TBTPLL_CFGCR0            0x16429C
 -#define TGL_DPLL_CFGCR0(pll)          _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
 -                                                _TGL_DPLL1_CFGCR0, \
 -                                                _TGL_TBTPLL_CFGCR0)
 +#define TGL_DPLL_CFGCR0(pll)          _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
 +                                            _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,     \
 +                                            _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
  #define RKL_DPLL_CFGCR0(pll)          _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
                                                  _TGL_DPLL1_CFGCR0)
  
@@@ -7192,36 -7317,40 +7183,36 @@@
  #define _TGL_DPLL0_CFGCR1             0x164288
  #define _TGL_DPLL1_CFGCR1             0x164290
  #define _TGL_TBTPLL_CFGCR1            0x1642A0
 -#define TGL_DPLL_CFGCR1(pll)          _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
 -                                                 _TGL_DPLL1_CFGCR1, \
 -                                                 _TGL_TBTPLL_CFGCR1)
 +#define TGL_DPLL_CFGCR1(pll)          _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
 +                                            _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,     \
 +                                            _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
  #define RKL_DPLL_CFGCR1(pll)          _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
                                                  _TGL_DPLL1_CFGCR1)
  
  #define _DG1_DPLL2_CFGCR0             0x16C284
  #define _DG1_DPLL3_CFGCR0             0x16C28C
 -#define DG1_DPLL_CFGCR0(pll)          _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
 -                                                 _TGL_DPLL1_CFGCR0, \
 -                                                 _DG1_DPLL2_CFGCR0, \
 -                                                 _DG1_DPLL3_CFGCR0)
 +#define DG1_DPLL_CFGCR0(pll)          _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
 +                                            _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,     \
 +                                            _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
  
  #define _DG1_DPLL2_CFGCR1               0x16C288
  #define _DG1_DPLL3_CFGCR1               0x16C290
 -#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
 -                                                 _TGL_DPLL1_CFGCR1, \
 -                                                 _DG1_DPLL2_CFGCR1, \
 -                                                 _DG1_DPLL3_CFGCR1)
 +#define DG1_DPLL_CFGCR1(pll)            _MMIO(_PICK_EVEN_2RANGES(pll, 2,              \
 +                                            _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,     \
 +                                            _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
  
  /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
 -#define _ADLS_DPLL3_CFGCR0            0x1642C0
  #define _ADLS_DPLL4_CFGCR0            0x164294
 -#define ADLS_DPLL_CFGCR0(pll)         _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
 -                                                 _TGL_DPLL1_CFGCR0, \
 -                                                 _ADLS_DPLL4_CFGCR0, \
 -                                                 _ADLS_DPLL3_CFGCR0)
 +#define _ADLS_DPLL3_CFGCR0            0x1642C0
 +#define ADLS_DPLL_CFGCR0(pll)         _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
 +                                            _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0,     \
 +                                            _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
  
 -#define _ADLS_DPLL3_CFGCR1            0x1642C4
  #define _ADLS_DPLL4_CFGCR1            0x164298
 -#define ADLS_DPLL_CFGCR1(pll)         _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
 -                                                 _TGL_DPLL1_CFGCR1, \
 -                                                 _ADLS_DPLL4_CFGCR1, \
 -                                                 _ADLS_DPLL3_CFGCR1)
 +#define _ADLS_DPLL3_CFGCR1            0x1642C4
 +#define ADLS_DPLL_CFGCR1(pll)         _MMIO(_PICK_EVEN_2RANGES(pll, 2,                \
 +                                            _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1,     \
 +                                            _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
  
  /* BXT display engine PLL */
  #define BXT_DE_PLL_CTL                        _MMIO(0x6d000)
@@@ -7554,6 -7683,44 +7545,6 @@@
  #define PIPE_FRMTMSTMP(pipe)          \
                        _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
  
 -/* Display Stream Splitter Control */
 -#define DSS_CTL1                              _MMIO(0x67400)
 -#define  SPLITTER_ENABLE                      (1 << 31)
 -#define  JOINER_ENABLE                                (1 << 30)
 -#define  DUAL_LINK_MODE_INTERLEAVE            (1 << 24)
 -#define  DUAL_LINK_MODE_FRONTBACK             (0 << 24)
 -#define  OVERLAP_PIXELS_MASK                  (0xf << 16)
 -#define  OVERLAP_PIXELS(pixels)                       ((pixels) << 16)
 -#define  LEFT_DL_BUF_TARGET_DEPTH_MASK                (0xfff << 0)
 -#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)     ((pixels) << 0)
 -#define  MAX_DL_BUFFER_TARGET_DEPTH           0x5a0
 -
 -#define DSS_CTL2                              _MMIO(0x67404)
 -#define  LEFT_BRANCH_VDSC_ENABLE              (1 << 31)
 -#define  RIGHT_BRANCH_VDSC_ENABLE             (1 << 15)
 -#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK               (0xfff << 0)
 -#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)    ((pixels) << 0)
 -
 -#define _ICL_PIPE_DSS_CTL1_PB                 0x78200
 -#define _ICL_PIPE_DSS_CTL1_PC                 0x78400
 -#define ICL_PIPE_DSS_CTL1(pipe)                       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_PIPE_DSS_CTL1_PB, \
 -                                                         _ICL_PIPE_DSS_CTL1_PC)
 -#define  BIG_JOINER_ENABLE                    (1 << 29)
 -#define  MASTER_BIG_JOINER_ENABLE             (1 << 28)
 -#define  VGA_CENTERING_ENABLE                 (1 << 27)
 -#define  SPLITTER_CONFIGURATION_MASK          REG_GENMASK(26, 25)
 -#define  SPLITTER_CONFIGURATION_2_SEGMENT     REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
 -#define  SPLITTER_CONFIGURATION_4_SEGMENT     REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
 -#define  UNCOMPRESSED_JOINER_MASTER           (1 << 21)
 -#define  UNCOMPRESSED_JOINER_SLAVE            (1 << 20)
 -
 -#define _ICL_PIPE_DSS_CTL2_PB                 0x78204
 -#define _ICL_PIPE_DSS_CTL2_PC                 0x78404
 -#define ICL_PIPE_DSS_CTL2(pipe)                       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_PIPE_DSS_CTL2_PB, \
 -                                                         _ICL_PIPE_DSS_CTL2_PC)
 -
  #define GGC                           _MMIO(0x108040)
  #define   GMS_MASK                    REG_GENMASK(15, 8)
  #define   GGMS_MASK                   REG_GENMASK(7, 6)
@@@ -7577,6 -7744,314 +7568,6 @@@
  #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN     (1 << 23)
  #define  DG2_PHY_DP_TX_ACK_MASK                       REG_GENMASK(23, 20)
  
 -/* Icelake Display Stream Compression Registers */
 -#define DSCA_PICTURE_PARAMETER_SET_0          _MMIO(0x6B200)
 -#define DSCC_PICTURE_PARAMETER_SET_0          _MMIO(0x6BA00)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB  0x78270
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB  0x78370
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC  0x78470
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC  0x78570
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
 -#define  DSC_ALT_ICH_SEL              (1 << 20)
 -#define  DSC_VBR_ENABLE                       (1 << 19)
 -#define  DSC_422_ENABLE                       (1 << 18)
 -#define  DSC_COLOR_SPACE_CONVERSION   (1 << 17)
 -#define  DSC_BLOCK_PREDICTION         (1 << 16)
 -#define  DSC_LINE_BUF_DEPTH_SHIFT     12
 -#define  DSC_BPC_SHIFT                        8
 -#define  DSC_VER_MIN_SHIFT            4
 -#define  DSC_VER_MAJ                  (0x1 << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_1          _MMIO(0x6B204)
 -#define DSCC_PICTURE_PARAMETER_SET_1          _MMIO(0x6BA04)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB  0x78274
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB  0x78374
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC  0x78474
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC  0x78574
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
 -#define  DSC_BPP(bpp)                         ((bpp) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_2          _MMIO(0x6B208)
 -#define DSCC_PICTURE_PARAMETER_SET_2          _MMIO(0x6BA08)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB  0x78278
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB  0x78378
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC  0x78478
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC  0x78578
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                          _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
 -                                          _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
 -#define  DSC_PIC_WIDTH(pic_width)     ((pic_width) << 16)
 -#define  DSC_PIC_HEIGHT(pic_height)   ((pic_height) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_3          _MMIO(0x6B20C)
 -#define DSCC_PICTURE_PARAMETER_SET_3          _MMIO(0x6BA0C)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB  0x7827C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB  0x7837C
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC  0x7847C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC  0x7857C
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
 -#define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
 -#define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_4          _MMIO(0x6B210)
 -#define DSCC_PICTURE_PARAMETER_SET_4          _MMIO(0x6BA10)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB  0x78280
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB  0x78380
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC  0x78480
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC  0x78580
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
 -#define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
 -#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_5          _MMIO(0x6B214)
 -#define DSCC_PICTURE_PARAMETER_SET_5          _MMIO(0x6BA14)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB  0x78284
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB  0x78384
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC  0x78484
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC  0x78584
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
 -#define  DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
 -#define  DSC_SCALE_INC_INT(scale_inc)         ((scale_inc) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_6          _MMIO(0x6B218)
 -#define DSCC_PICTURE_PARAMETER_SET_6          _MMIO(0x6BA18)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB  0x78288
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB  0x78388
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC  0x78488
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC  0x78588
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
 -#define  DSC_FLATNESS_MAX_QP(max_qp)          ((max_qp) << 24)
 -#define  DSC_FLATNESS_MIN_QP(min_qp)          ((min_qp) << 16)
 -#define  DSC_FIRST_LINE_BPG_OFFSET(offset)    ((offset) << 8)
 -#define  DSC_INITIAL_SCALE_VALUE(value)               ((value) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_7          _MMIO(0x6B21C)
 -#define DSCC_PICTURE_PARAMETER_SET_7          _MMIO(0x6BA1C)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB  0x7828C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB  0x7838C
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC  0x7848C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC  0x7858C
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                          _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
 -                                                          _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                          _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
 -                                                          _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
 -#define  DSC_NFL_BPG_OFFSET(bpg_offset)               ((bpg_offset) << 16)
 -#define  DSC_SLICE_BPG_OFFSET(bpg_offset)     ((bpg_offset) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_8          _MMIO(0x6B220)
 -#define DSCC_PICTURE_PARAMETER_SET_8          _MMIO(0x6BA20)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB  0x78290
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB  0x78390
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC  0x78490
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC  0x78590
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
 -#define  DSC_INITIAL_OFFSET(initial_offset)           ((initial_offset) << 16)
 -#define  DSC_FINAL_OFFSET(final_offset)                       ((final_offset) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_9          _MMIO(0x6B224)
 -#define DSCC_PICTURE_PARAMETER_SET_9          _MMIO(0x6BA24)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB  0x78294
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB  0x78394
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC  0x78494
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC  0x78594
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)        _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
 -#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)     ((rc_edge_fact) << 16)
 -#define  DSC_RC_MODEL_SIZE(rc_model_size)     ((rc_model_size) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_10         _MMIO(0x6B228)
 -#define DSCC_PICTURE_PARAMETER_SET_10         _MMIO(0x6BA28)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
 -#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)                ((rc_tgt_off_low) << 20)
 -#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)      ((rc_tgt_off_high) << 16)
 -#define  DSC_RC_QUANT_INC_LIMIT1(lim)                 ((lim) << 8)
 -#define  DSC_RC_QUANT_INC_LIMIT0(lim)                 ((lim) << 0)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_11         _MMIO(0x6B22C)
 -#define DSCC_PICTURE_PARAMETER_SET_11         _MMIO(0x6BA2C)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_12         _MMIO(0x6B260)
 -#define DSCC_PICTURE_PARAMETER_SET_12         _MMIO(0x6BA60)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_13         _MMIO(0x6B264)
 -#define DSCC_PICTURE_PARAMETER_SET_13         _MMIO(0x6BA64)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_14         _MMIO(0x6B268)
 -#define DSCC_PICTURE_PARAMETER_SET_14         _MMIO(0x6BA68)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_15         _MMIO(0x6B26C)
 -#define DSCC_PICTURE_PARAMETER_SET_15         _MMIO(0x6BA6C)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
 -
 -#define DSCA_PICTURE_PARAMETER_SET_16         _MMIO(0x6B270)
 -#define DSCC_PICTURE_PARAMETER_SET_16         _MMIO(0x6BA70)
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
 -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
 -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
 -#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
 -                                                         _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
 -#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)       _MMIO_PIPE((pipe) - PIPE_B, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
 -                                                         _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
 -#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
 -#define  DSC_SLICE_PER_LINE(slice_per_line)           ((slice_per_line) << 16)
 -#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)               ((slice_chunk_size) << 0)
 -
 -/* Icelake Rate Control Buffer Threshold Registers */
 -#define DSCA_RC_BUF_THRESH_0                  _MMIO(0x6B230)
 -#define DSCA_RC_BUF_THRESH_0_UDW              _MMIO(0x6B230 + 4)
 -#define DSCC_RC_BUF_THRESH_0                  _MMIO(0x6BA30)
 -#define DSCC_RC_BUF_THRESH_0_UDW              _MMIO(0x6BA30 + 4)
 -#define _ICL_DSC0_RC_BUF_THRESH_0_PB          (0x78254)
 -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB      (0x78254 + 4)
 -#define _ICL_DSC1_RC_BUF_THRESH_0_PB          (0x78354)
 -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB      (0x78354 + 4)
 -#define _ICL_DSC0_RC_BUF_THRESH_0_PC          (0x78454)
 -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC      (0x78454 + 4)
 -#define _ICL_DSC1_RC_BUF_THRESH_0_PC          (0x78554)
 -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC      (0x78554 + 4)
 -#define ICL_DSC0_RC_BUF_THRESH_0(pipe)                _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_0_PB, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_0_PC)
 -#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe)    _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
 -#define ICL_DSC1_RC_BUF_THRESH_0(pipe)                _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_0_PB, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_0_PC)
 -#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe)    _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
 -
 -#define DSCA_RC_BUF_THRESH_1                  _MMIO(0x6B238)
 -#define DSCA_RC_BUF_THRESH_1_UDW              _MMIO(0x6B238 + 4)
 -#define DSCC_RC_BUF_THRESH_1                  _MMIO(0x6BA38)
 -#define DSCC_RC_BUF_THRESH_1_UDW              _MMIO(0x6BA38 + 4)
 -#define _ICL_DSC0_RC_BUF_THRESH_1_PB          (0x7825C)
 -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB      (0x7825C + 4)
 -#define _ICL_DSC1_RC_BUF_THRESH_1_PB          (0x7835C)
 -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB      (0x7835C + 4)
 -#define _ICL_DSC0_RC_BUF_THRESH_1_PC          (0x7845C)
 -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC      (0x7845C + 4)
 -#define _ICL_DSC1_RC_BUF_THRESH_1_PC          (0x7855C)
 -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC      (0x7855C + 4)
 -#define ICL_DSC0_RC_BUF_THRESH_1(pipe)                _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_1_PB, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_1_PC)
 -#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe)    _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
 -                                              _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
 -#define ICL_DSC1_RC_BUF_THRESH_1(pipe)                _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_1_PB, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_1_PC)
 -#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe)    _MMIO_PIPE((pipe) - PIPE_B, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
 -                                              _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
 -
  #define PORT_TX_DFLEXDPSP(fia)                        _MMIO_FIA((fia), 0x008A0)
  #define   MODULAR_FIA_MASK                    (1 << 4)
  #define   TC_LIVE_STATE_TBT(idx)              (1 << ((idx) * 8 + 6))
@@@ -7620,54 -8095,8 +7611,54 @@@
  #define DSB_HEAD(pipe, id)            _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
  #define DSB_TAIL(pipe, id)            _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
  #define DSB_CTRL(pipe, id)            _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
 -#define   DSB_ENABLE                  (1 << 31)
 -#define   DSB_STATUS                  (1 << 0)
 +#define   DSB_ENABLE                  REG_BIT(31)
 +#define   DSB_BUF_REITERATE           REG_BIT(29)
 +#define   DSB_WAIT_FOR_VBLANK         REG_BIT(28)
 +#define   DSB_WAIT_FOR_LINE_IN                REG_BIT(27)
 +#define   DSB_HALT                    REG_BIT(16)
 +#define   DSB_NON_POSTED              REG_BIT(8)
 +#define   DSB_STATUS_BUSY             REG_BIT(0)
 +#define DSB_MMIOCTRL(pipe, id)                _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
 +#define   DSB_MMIO_DEAD_CLOCKS_ENABLE REG_BIT(31)
 +#define   DSB_MMIO_DEAD_CLOCKS_COUNT_MASK     REG_GENMASK(15, 8)
 +#define   DSB_MMIO_DEAD_CLOCKS_COUNT(x)       REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
 +#define   DSB_MMIO_CYCLES_MASK                REG_GENMASK(7, 0)
 +#define   DSB_MMIO_CYCLES(x)          REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
 +#define DSB_POLLFUNC(pipe, id)                _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
 +#define   DSB_POLL_ENABLE             REG_BIT(31)
 +#define   DSB_POLL_WAIT_MASK          REG_GENMASK(30, 23)
 +#define   DSB_POLL_WAIT(x)            REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
 +#define   DSB_POLL_COUNT_MASK         REG_GENMASK(22, 15)
 +#define   DSB_POLL_COUNT(x)           REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
 +#define DSB_DEBUG(pipe, id)           _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
 +#define DSB_POLLMASK(pipe, id)                _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
 +#define DSB_STATUS(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
 +#define DSB_INTERRUPT(pipe, id)               _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
 +#define   DSB_ATS_FAULT_INT_EN                REG_BIT(20)
 +#define   DSB_GTT_FAULT_INT_EN                REG_BIT(19)
 +#define   DSB_RSPTIMEOUT_INT_EN               REG_BIT(18)
 +#define   DSB_POLL_ERR_INT_EN         REG_BIT(17)
 +#define   DSB_PROG_INT_EN             REG_BIT(16)
 +#define   DSB_ATS_FAULT_INT_STATUS    REG_BIT(4)
 +#define   DSB_GTT_FAULT_INT_STATUS    REG_BIT(3)
 +#define   DSB_RSPTIMEOUT_INT_STATUS   REG_BIT(2)
 +#define   DSB_POLL_ERR_INT_STATUS     REG_BIT(1)
 +#define   DSB_PROG_INT_STATUS         REG_BIT(0)
 +#define DSB_CURRENT_HEAD(pipe, id)    _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
 +#define DSB_RM_TIMEOUT(pipe, id)      _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)
 +#define   DSB_RM_CLAIM_TIMEOUT                REG_BIT(31)
 +#define   DSB_RM_READY_TIMEOUT                REG_BIT(30)
 +#define   DSB_RM_CLAIM_TIMEOUT_COUNT_MASK     REG_GENMASK(23, 16)
 +#define   DSB_RM_CLAIM_TIMEOUT_COUNT(x)       REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */
 +#define   DSB_RM_READY_TIMEOUT_VALUE_MASK     REG_GENMASK(15, 0)
 +#define   DSB_RM_READY_TIMEOUT_VALUE(x)       REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
 +#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id)    _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
 +#define DSB_PMCTRL(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
 +#define DSB_PMCTRL_2(pipe, id)                _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
 +#define DSB_PF_LN_LOWER(pipe, id)     _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
 +#define DSB_PF_LN_UPPER(pipe, id)     _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
 +#define DSB_BUFRPT_CNT(pipe, id)      _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
 +#define DSB_CHICKEN(pipe, id)         _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
  
  #define CLKREQ_POLICY                 _MMIO(0x101038)
  #define  CLKREQ_POLICY_MEM_UP_OVRD    REG_BIT(1)

diff --combined drivers/gpu/drm/i915/intel_uncore.c
index f4b3b20630182f040b02979e8a0c28c5b476fc77,7894447c2858782796d72cd6726818972277a4ef..e1e1f34490c8e465765c8a460b6dd667051325a6
--- 1/drivers/gpu/drm/i915/intel_uncore.c
--- 2/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -32,6 -32,7 +32,6 @@@
  #include "i915_reg.h"
  #include "i915_trace.h"
  #include "i915_vgpu.h"
 -#include "intel_pm.h"
  
  #define FORCEWAKE_ACK_TIMEOUT_MS 50
  #define GT_FIFO_TIMEOUT_MS     10
@@@ -2459,7 -2460,7 +2459,7 @@@ static int i915_pmic_bus_access_notifie
  
  static void uncore_unmap_mmio(struct drm_device *drm, void *regs)
  {
 -      iounmap(regs);
 +      iounmap((void __iomem *)regs);
  }
  
  int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
@@@ -2490,8 -2491,7 +2490,8 @@@
                return -EIO;
        }
  
 -      return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio, uncore->regs);
 +      return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio,
 +                                      (void __force *)uncore->regs);
  }
  
  void intel_uncore_init_early(struct intel_uncore *uncore,
@@@ -2748,14 -2748,25 +2748,25 @@@ static void driver_initiated_flr(struc
        /* Trigger the actual Driver-FLR */
        intel_uncore_rmw_fw(uncore, GU_CNTL, 0, DRIVERFLR);
  
+       /* Wait for hardware teardown to complete */
+       ret = intel_wait_for_register_fw(uncore, GU_CNTL,
+                                        DRIVERFLR, 0,
+                                        flr_timeout_ms);
+       if (ret) {
+               drm_err(&i915->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret);
+               return;
+       }
+ 
+       /* Wait for hardware/firmware re-init to complete */
        ret = intel_wait_for_register_fw(uncore, GU_DEBUG,
                                         DRIVERFLR_STATUS, DRIVERFLR_STATUS,
                                         flr_timeout_ms);
        if (ret) {
-               drm_err(&i915->drm, "wait for Driver-FLR completion failed! %d\n", ret);
+               drm_err(&i915->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret);
                return;
        }
  
+       /* Clear sticky completion status */
        intel_uncore_write_fw(uncore, GU_DEBUG, DRIVERFLR_STATUS);
  }