i7core_edac: Add a code to probe Xeon 55xx bus

This code changes the detection procedure of i7core_edac. Instead of
directly probing for MC registers, it probes for another register found
on Nehalem. If found, it tries to pick the first MC PCI BUS. This should
work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255
that are not properly detected by the non-legacy PCI methods.

The new detection code scans specifically at buses 254 and 255 for the
Xeon 55xx devices.

This code has not tested yet. After working, a change at the code will
be needed, since the i7core is not yet ready for working with 2 sets of
MC.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index c734c277b116047b1d0f4e8ee23f6c12294efca4..d6cc2eddf33968b3de2d7fb262d010e66664d274 100644 (file)
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -57,6 +57,7 @@ void pcibios_scan_specific_bus(int busn)
                }
        }
 }
+EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus);
 
 int __init pci_subsys_init(void)
 {

diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 26cd5c924d56927446da79fcc147438f46d0c005..eec0c13c0205fe46dd1ba6850a107f22449ff503 100644 (file)
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -221,15 +221,15 @@ struct i7core_dev_info {
        .dev_id = (device_id)
 
 struct pci_id_descr pci_devs[] = {
+               /* Generic Non-core registers */
+       { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE)  },
+
                /* Memory controller */
        { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
        { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
        { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS)  }, /* if RDIMM is supported */
        { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
 
-               /* Generic Non-core registers */
-       { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE)  },
-
                /* Channel 0 */
        { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
        { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
@@ -255,7 +255,7 @@ struct pci_id_descr pci_devs[] = {
  * This should match the first device at pci_devs table
  */
 static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
-       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7_MCR)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
        {0,}                    /* 0 terminated list. */
 };
 
@@ -1069,6 +1069,15 @@ static int i7core_get_devices(void)
        for (i = 0; i < N_DEVS; i++) {
                pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
                                        pci_devs[i].dev_id, NULL);
+
+               if (!pdev && !i) {
+                       pcibios_scan_specific_bus(254);
+                       pcibios_scan_specific_bus(255);
+
+                       pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                               pci_devs[i].dev_id, NULL);
+               }
+
                if (likely(pdev))
                        pci_devs[i].pdev = pdev;
                else {

diff --git a/include/linux/pci.h b/include/linux/pci.h
index a788fa12ff310b7831587ebc4565e01d5e76d726..5e2c7e15187dc9bc050b156cafcbb249cae339e9 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -621,6 +621,7 @@ void pci_fixup_cardbus(struct pci_bus *);
 
 /* Generic PCI functions used internally */
 
+void pcibios_scan_specific_bus(int busn);
 extern struct pci_bus *pci_find_bus(int domain, int busnr);
 void pci_bus_add_devices(const struct pci_bus *bus);
 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 9d5bfe86ba73a52d013bf977808385d62f02ab4a..12c3da6ef14d6ddb67cf3eb7547346a51f6ba778 100644 (file)
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2554,6 +2554,7 @@
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG5  0x342a
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG6  0x342b
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG7  0x342c
+#define PCI_DEVICE_ID_INTEL_X58_HUB_MGMT 0x342e
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG0  0x3430
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG1  0x3431
 #define PCI_DEVICE_ID_INTEL_IOAT_TBG2  0x3432