drm/i915: Fix for PHY_MISC_TC1 offset

Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
available. Just correct the offset of the last phy to 0x64C14 as the
rest of the support for it is coming on next commits.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-1-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 8fd00de981fc6a4e712845a1855531d3a4a4194f..4cdce0116883811d07eea94576e9a800a33ae0c6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915)
                if (!intel_phy_is_snps(i915, phy))
                        continue;
 
-               if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
+               if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
                                            DG2_PHY_DP_TX_ACK_MASK, 25))
                        drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n",
                                phy_name(phy));

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de403ee18bc70c68f74b9d3cbf6d3ab1e4408d0f..c6095c33a3317b63b2a3c16394a89779cfbe6155 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9361,8 +9361,10 @@ enum skl_power_gate {
 
 #define _ICL_PHY_MISC_A                0x64C00
 #define _ICL_PHY_MISC_B                0x64C04
-#define ICL_PHY_MISC(port)     _MMIO_PORT(port, _ICL_PHY_MISC_A, \
-                                                _ICL_PHY_MISC_B)
+#define _DG2_PHY_MISC_TC1      0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
+#define ICL_PHY_MISC(port)     _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
+#define DG2_PHY_MISC(port)     ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+                                ICL_PHY_MISC(port))
 #define  ICL_PHY_MISC_MUX_DDID                 (1 << 28)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN      (1 << 23)
 #define  DG2_PHY_DP_TX_ACK_MASK                        REG_GENMASK(23, 20)