drm/amdgpu/pm: Fix the null pointer dereference in apply_state_adjust_rules
authorMa Jun <Jun.Ma2@amd.com>
Thu, 9 May 2024 07:51:35 +0000 (15:51 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 17 May 2024 21:40:36 +0000 (17:40 -0400)
Check the pointer value to fix potential null pointer
dereference

Acked-by: Yang Wang<kevinyang.wang@amd.com>
Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

index 9301e65ff13c98694189784890b1180fff57c8f2..632a25957477ee45151f7b51977af387d7719439 100644 (file)
@@ -3314,8 +3314,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                        const struct pp_power_state *current_ps)
 {
        struct amdgpu_device *adev = hwmgr->adev;
-       struct smu7_power_state *smu7_ps =
-                               cast_phw_smu7_power_state(&request_ps->hardware);
+       struct smu7_power_state *smu7_ps;
        uint32_t sclk;
        uint32_t mclk;
        struct PP_Clocks minimum_clocks = {0};
@@ -3332,6 +3331,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
        uint32_t latency;
        bool latency_allowed = false;
 
+       smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);
+       if (!smu7_ps)
+               return -EINVAL;
+
        data->battery_state = (PP_StateUILabel_Battery ==
                        request_ps->classification.ui_label);
        data->mclk_ignore_signal = false;
index b858cc2a5c9ef53d93ecbe37aec85b00d72e81d5..7e11974208732547ac7e0030a15c3a680370cce3 100644 (file)
@@ -1074,16 +1074,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                                struct pp_power_state  *prequest_ps,
                        const struct pp_power_state *pcurrent_ps)
 {
-       struct smu8_power_state *smu8_ps =
-                               cast_smu8_power_state(&prequest_ps->hardware);
-
-       const struct smu8_power_state *smu8_current_ps =
-                               cast_const_smu8_power_state(&pcurrent_ps->hardware);
-
+       struct smu8_power_state *smu8_ps;
+       const struct smu8_power_state *smu8_current_ps;
        struct smu8_hwmgr *data = hwmgr->backend;
        struct PP_Clocks clocks = {0, 0, 0, 0};
        bool force_high;
 
+       smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);
+       smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);
+
+       if (!smu8_ps || !smu8_current_ps)
+               return -EINVAL;
+
        smu8_ps->need_dfs_bypass = true;
 
        data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
index 3b461c07344b833eba07e25b9af5f2e1af1f99dc..6524d99e5cab0cae04ad0473cf08bf0e62282d4c 100644 (file)
@@ -3280,8 +3280,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                        const struct pp_power_state *current_ps)
 {
        struct amdgpu_device *adev = hwmgr->adev;
-       struct vega10_power_state *vega10_ps =
-                               cast_phw_vega10_power_state(&request_ps->hardware);
+       struct vega10_power_state *vega10_ps;
        uint32_t sclk;
        uint32_t mclk;
        struct PP_Clocks minimum_clocks = {0};
@@ -3299,6 +3298,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
        uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
        uint32_t latency;
 
+       vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);
+       if (!vega10_ps)
+               return -EINVAL;
+
        data->battery_state = (PP_StateUILabel_Battery ==
                        request_ps->classification.ui_label);