drm/xe: Add build on bug to assert access counter queue works
authorMatthew Brost <matthew.brost@intel.com>
Wed, 10 Jan 2024 01:24:38 +0000 (17:24 -0800)
committerMatthew Brost <matthew.brost@intel.com>
Wed, 10 Jan 2024 23:11:22 +0000 (15:11 -0800)
If ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW != 0 then the access counter queue
logic does not work when wrapping occurs. Add a build bug on to assert
ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0 to enforce this restriction and
document the code.

v2:
- s/NUM_ACC_QUEUE/ACC_QUEUE_NUM_DW (Brian)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/xe/xe_gt_pagefault.c

index 3ca715e2ec19eca247f10e6b9f2e885404e97db1..13183088401f65d34b2ba6c43dd8f2ab5884c7c6 100644 (file)
@@ -629,6 +629,11 @@ int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len)
        u32 asid;
        bool full;
 
+       /*
+        * The below logic doesn't work unless ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0
+        */
+       BUILD_BUG_ON(ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW);
+
        if (unlikely(len != ACC_MSG_LEN_DW))
                return -EPROTO;