arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP

Add PCIe EP support for i.MX8QM and i.MX8QXP.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 577a8b112ca5c24a43322b333f78d910b38da779..9b8b1380c4c2bb25f691d72a0217915cf3824889 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -80,6 +80,25 @@ hsio_subsys: bus@5f000000 {
                status = "disabled";
        };
 
+       pcieb_ep: pcie-ep@5f010000 {
+               compatible = "fsl,imx8q-pcie-ep";
+               reg = <0x5f010000 0x00010000>,
+                     <0x80000000 0x10000000>;
+               reg-names = "dbi", "addr_space";
+               num-lanes = <1>;
+               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "dma";
+               clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
+                        <&pcieb_lpcg IMX_LPCG_CLK_4>,
+                        <&pcieb_lpcg IMX_LPCG_CLK_5>;
+               clock-names = "dbi", "mstr", "slv";
+               power-domains = <&pd IMX_SC_R_PCIE_B>;
+               fsl,max-link-speed = <3>;
+               num-ib-windows = <6>;
+               num-ob-windows = <6>;
+               status = "disabled";
+       };
+
        pcieb_lpcg: clock-controller@5f060000 {
                compatible = "fsl,imx8qxp-lpcg";
                reg = <0x5f060000 0x10000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index b1d0189a1725895404fe168d3ed80eef0a6e1e24..d52609e4fc4552c4b068a7e86b59683e0fe28a3a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -42,6 +42,25 @@
                status = "disabled";
        };
 
+       pciea_ep: pcie-ep@5f000000 {
+               compatible = "fsl,imx8q-pcie-ep";
+               reg = <0x5f000000 0x00010000>,
+                     <0x40000000 0x10000000>;
+               reg-names = "dbi", "addr_space";
+               num-lanes = <1>;
+               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "dma";
+               clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
+                        <&pciea_lpcg IMX_LPCG_CLK_4>,
+                        <&pciea_lpcg IMX_LPCG_CLK_5>;
+               clock-names = "dbi", "mstr", "slv";
+               power-domains = <&pd IMX_SC_R_PCIE_A>;
+               fsl,max-link-speed = <3>;
+               num-ib-windows = <6>;
+               num-ob-windows = <6>;
+               status = "disabled";
+       };
+
        pcieb: pcie@5f010000 {
                compatible = "fsl,imx8q-pcie";
                reg = <0x5f010000 0x10000>,