drm/i915/vga: Add more VGACNTRL bits

Define a pile of extra VGACNTRL bits. We don't really have
any real use for most of these but nicer to have them all
in one place rather than trawling the specs when one wants
to know what's in there.

I will have some real use for the CHV pipe select bits later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5430fb0be0332b290b32c4eb7359c1929cd73f88..e9491f12876f2563b22d61c588d140d1aa977eb4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1778,9 +1778,26 @@
 /* VBIOS regs */
 #define VGACNTRL               _MMIO(0x71400)
 #define   VGA_DISP_DISABLE                     REG_BIT(31)
-#define   VGA_2X_MODE                          REG_BIT(30)
-#define   VGA_PIPE_SEL_MASK                    REG_BIT(29)
+#define   VGA_2X_MODE                          REG_BIT(30) /* pre-ilk */
+#define   VGA_PIPE_SEL_MASK                    REG_BIT(29) /* pre-ivb */
 #define   VGA_PIPE_SEL(pipe)                   REG_FIELD_PREP(VGA_PIPE_SEL_MASK, (pipe))
+#define   VGA_PIPE_SEL_MASK_CHV                        REG_GENMASK(29, 28) /* chv */
+#define   VGA_PIPE_SEL_CHV(pipe)               REG_FIELD_PREP(VGA_PIPE_SEL_MASK_CHV, (pipe))
+#define   VGA_BORDER_ENABLE                    REG_BIT(26)
+#define   VGA_PIPE_CSC_ENABLE                  REG_BIT(24) /* ilk+ */
+#define   VGA_CENTERING_ENABLE_MASK            REG_GENMASK(25, 24) /* pre-ilk */
+#define   VGA_PALETTE_READ_SEL                 REG_BIT(23) /* pre-ivb */
+#define   VGA_PALETTE_A_WRITE_DISABLE          REG_BIT(22) /* pre-ivb */
+#define   VGA_PALETTE_B_WRITE_DISABLE          REG_BIT(21) /* pre-ivb */
+#define   VGA_LEGACY_8BIT_PALETTE_ENABLE       REG_BIT(20)
+#define   VGA_PALETTE_BYPASS                   REG_BIT(19)
+#define   VGA_NINE_DOT_DISABLE                 REG_BIT(18)
+#define   VGA_PALETTE_READ_SEL_HI_CHV          REG_BIT(15) /* chv */
+#define   VGA_PALETTE_C_WRITE_DISABLE_CHV      REG_BIT(14) /* chv */
+#define   VGA_ACTIVE_THROTTLING_MASK           REG_GENMASK(15, 12) /* ilk+ */
+#define   VGA_BLANK_THROTTLING_MASK            REG_GENMASK(11, 8) /* ilk+ */
+#define   VGA_BLINK_DUTY_CYCLE_MASK            REG_GENMASK(7, 6)
+#define   VGA_VSYNC_BLINK_RATE_MASK            REG_GENMASK(5, 0)
 
 #define VLV_VGACNTRL           _MMIO(VLV_DISPLAY_BASE + 0x71400)