arm64: Cleanup __cpu_set_tcr_t0sz()

The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode
the virtual address space translated by TTBR0_EL1. When updating the
field, for example because we are switching to/from the idmap page-table,
__cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted,
resulting in harmless but confusing double shifts by 0 in the code.

Co-developed-by: Leem ChaeHoon <infinite.run@gmail.com>
Signed-off-by: Leem ChaeHoon <infinite.run@gmail.com>
Signed-off-by: Seongsu Park <sgsu.park@samsung.com>
Link: https://lore.kernel.org/r/20240523122146.144483-1-sgsu.park@samsung.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index c768d16b81a49e5a4718fb9fd7d3075028d92def..bd19f4c758b779e884ea581913c406a0828d0ec9 100644 (file)
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
 {
        unsigned long tcr = read_sysreg(tcr_el1);
 
-       if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
+       if ((tcr & TCR_T0SZ_MASK) == t0sz)
                return;
 
        tcr &= ~TCR_T0SZ_MASK;
-       tcr |= t0sz << TCR_T0SZ_OFFSET;
+       tcr |= t0sz;
        write_sysreg(tcr, tcr_el1);
        isb();
 }