drm/amdgpu/mes11: update mes_reset_queue function to support sdma queue

Reset sdma queue through mmio based on me_id and queue_id.

v2: simplify callflows and register calculation.

Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 10b61ff63802cad56b7fca1b3e4c9d56183dcbee..aab9632a06cea4e3f648f85b23937ddbf79effaf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -905,7 +905,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
        queue_input.me_id = ring->me;
        queue_input.pipe_id = ring->pipe;
        queue_input.queue_id = ring->queue;
-       queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+       queue_input.mqd_addr = ring->mqd_obj ? amdgpu_bo_gpu_offset(ring->mqd_obj) : 0;
        queue_input.wptr_addr = ring->wptr_gpu_addr;
        queue_input.vmid = vmid;
        queue_input.use_mmio = use_mmio;

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 231a3d490ea8e3c4eb4ea998d2d7673a200700e7..e2b3f859a1c0536ea1e278964caf6459a70e4b41 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -366,7 +366,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ
                                      uint32_t queue_id, uint32_t vmid)
 {
        struct amdgpu_device *adev = mes->adev;
-       uint32_t value;
+       uint32_t value, reg;
        int i, r = 0;
 
        amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
@@ -424,6 +424,31 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ
                }
                soc21_grbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
+       } else if (queue_type == AMDGPU_RING_TYPE_SDMA) {
+               dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n",
+                        me_id, pipe_id, queue_id);
+               switch (me_id) {
+               case 1:
+                       reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);
+                       break;
+               case 0:
+               default:
+                       reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);
+                       break;
+               }
+
+               value = 1 << queue_id;
+               WREG32(reg, value);
+               /* wait for queue reset done */
+               for (i = 0; i < adev->usec_timeout; i++) {
+                       if (!(RREG32(reg) & value))
+                               break;
+                       udelay(1);
+               }
+               if (i >= adev->usec_timeout) {
+                       dev_err(adev->dev, "failed to wait on sdma queue reset done\n");
+                       r = -ETIMEDOUT;
+               }
        }
 
        amdgpu_gfx_rlc_exit_safe_mode(adev, 0);