static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
if (cz_hwmgr->max_sclk_level == 0) {
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct amdgpu_device *adev = hwmgr->adev;
cz_hwmgr->gfx_ramp_step = 256*25/100;
static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
struct phm_clock_and_voltage_limits *table)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
struct phm_clock_voltage_dependency_table *dep_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
uint32_t i;
int result = 0;
static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->boot_power_level.engineClock =
cz_hwmgr->sys_info.bootup_engine_clock;
static int cz_init_sclk_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
unsigned long clock = 0, level;
static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_uvd_clock_voltage_dependency_table *table =
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
unsigned long clock = 0, level;
static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_vce_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
unsigned long clock = 0, level;
static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_acp_clock_voltage_dependency_table *table =
hwmgr->dyn_state.acp_clock_voltage_dependency_table;
unsigned long clock = 0, level;
static void cz_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->uvd_power_gated = false;
cz_hwmgr->vce_power_gated = false;
static void cz_init_sclk_threshold(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->low_sclk_interrupt_threshold = 0;
}
static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr =
- (struct cz_hwmgr *)(hwmgr->backend);
+ hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetWatermarkFrequency,
static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
if (hw_data->is_nb_dpm_enabled) {
if (enable) {
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
unsigned long dpm_features = 0;
if (cz_hwmgr->is_nb_dpm_enabled) {
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
unsigned long dpm_features = 0;
if (!cz_hwmgr->is_nb_dpm_enabled) {
{
bool disable_switch;
bool enable_low_mem_state;
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
static void cz_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
hw_data->disp_clk_bypass_pending = false;
hw_data->disp_clk_bypass = false;
static void cz_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
hw_data->is_nb_dpm_enabled = false;
}
static void cz_reset_cc6_data(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
hw_data->cc6_settings.cc6_setting_changed = false;
hw_data->cc6_settings.cpu_pstate_separation_time = 0;
static int cz_start_dpm(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
{
int ret = 0;
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
unsigned long dpm_features = 0;
if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
static void cz_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->acp_boot_level = 0xff;
}
const struct cz_power_state *cz_current_ps =
cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct PP_Clocks clocks = {0, 0, 0, 0};
bool force_high;
uint32_t num_of_active_displays = 0;
static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
unsigned long clock = 0, level;
static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
static int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_vce_clock_voltage_dependency_table *ptable =
hwmgr->dyn_state.vce_clock_voltage_dependency_table;
static uint32_t cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
return cz_hwmgr->sys_info.bootup_uma_clock;
}
static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
struct pp_hw_power_state *hw_ps)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
cz_ps->level = 1;
static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
uint32_t data = 0;
if (hw_data->cc6_settings.cc6_setting_changed) {
static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
{
- struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *hw_data = hwmgr->backend;
if (separation_time !=
hw_data->cc6_settings.cpu_pstate_separation_time ||
static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
- struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *data = hwmgr->backend;
struct phm_clock_voltage_dependency_table *sclk_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
int i, now, size = 0;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
- data = (struct cz_hwmgr *)(hwmgr->backend);
+ data = hwmgr->backend;
ps = cast_const_PhwCzPowerState(state);
level_index = index > ps->level - 1 ? ps->level - 1 : index;
static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
struct amd_pp_clocks *clocks)
{
- struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *data = hwmgr->backend;
int i;
struct phm_clock_voltage_dependency_table *table;
static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_clock_voltage_dependency_table *table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
static int cz_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
struct PP_TemperatureRange *thermal_data)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
static int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
uint32_t dpm_features = 0;
if (enable &&
int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
struct phm_uvd_clock_voltage_dependency_table *ptable =
hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
static int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
uint32_t dpm_features = 0;
if (enable && phm_cap_enabled(
static void cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
cz_hwmgr->uvd_power_gated = bgate;
static void cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
{
- struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+ struct cz_hwmgr *cz_hwmgr = hwmgr->backend;
if (bgate) {
cgs_set_powergating_state(
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ cz_smu = hwmgr->smu_backend;
ret = cgs_get_firmware_info(hwmgr->device,
CGS_UCODE_ID_CP_MEC, &info);
uint8_t type, bool is_last)
{
uint8_t i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
bool is_last)
{
uint8_t i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
struct SMU_Task *task = &toc->tasks[cz_smu->toc_entry_used_count++];
static int cz_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
cz_smu->toc_entry_aram = cz_smu->toc_entry_used_count;
cz_smu_populate_single_scratch_task(hwmgr,
static int cz_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
{
int i;
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
for (i = 0; i < NUM_JOBLIST_ENTRIES; i++)
static int cz_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_SAVE] = (uint8_t)cz_smu->toc_entry_used_count;
static int cz_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
struct TOC *toc = (struct TOC *)cz_smu->toc_buffer.kaddr;
toc->JobList[JOB_GFX_RESTORE] = (uint8_t)cz_smu->toc_entry_used_count;
static int cz_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
cz_smu->toc_entry_power_profiling_index = cz_smu->toc_entry_used_count;
static int cz_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
cz_smu->toc_entry_initialize_index = cz_smu->toc_entry_used_count;
static int cz_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
cz_smu->toc_entry_clock_table = cz_smu->toc_entry_used_count;
static int cz_smu_construct_toc(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
cz_smu->toc_entry_used_count = 0;
cz_smu_initialize_toc_empty_job_list(hwmgr);
static int cz_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
uint32_t firmware_type;
uint32_t i;
int ret;
uint32_t ulsize_byte,
struct cz_buffer_entry *entry)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
uint32_t ulsize_aligned = SIZE_ALIGN_32(ulsize_byte);
entry->data_size = ulsize_byte;
static int cz_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
static int cz_upload_pptable_settings(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
unsigned long i;
for (i = 0; i < cz_smu->scratch_buffer_length; i++) {
static int cz_request_smu_load_fw(struct pp_hwmgr *hwmgr)
{
- struct cz_smumgr *cz_smu = (struct cz_smumgr *)(hwmgr->smu_backend);
+ struct cz_smumgr *cz_smu = hwmgr->smu_backend;
uint32_t smc_address;
if (!hwmgr->reload_fw) {
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
- cz_smu = (struct cz_smumgr *)hwmgr->smu_backend;
+ cz_smu = hwmgr->smu_backend;
if (cz_smu) {
amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
&cz_smu->toc_buffer.mc_addr,