drm/amd/display: Remove redundant checks for pipe_ctx->stream

[WHAT & HOW]
The null checks for pipe_ctx->stream and pipe_ctx->stream_res.tg
are redundant as they were already dereferenced previously, as
reported by Coverity; therefore the null checks are removed.

This fixes 6 REVERSE_INULL issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 82d1ded095611439aca0235a269231cd59859153..4d359bb9b1ec00b254f8d5256653a340b520e2c4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -974,8 +974,8 @@ enum dc_status dcn20_enable_stream_timing(
        /* TODO enable stream if timing changed */
        /* TODO unblank stream if DP */
 
-       if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
-               if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
+       if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
+               if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
                        pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
        }
 
@@ -1827,8 +1827,7 @@ static void dcn20_update_dchubp_dpp(
        if (pipe_ctx->update_flags.bits.enable)
                hubp->funcs->set_blank(hubp, false);
        /* If the stream paired with this plane is phantom, the plane is also phantom */
-       if (pipe_ctx->stream && pipe_mall_type == SUBVP_PHANTOM
-                       && hubp->funcs->phantom_hubp_post_enable)
+       if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable)
                hubp->funcs->phantom_hubp_post_enable(hubp);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 8d0da56e4cc51b0c33df367547df665bdac44651..0cf55f557c3c33804baf21b439d6f24a93b08f9b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -916,8 +916,8 @@ enum dc_status dcn401_enable_stream_timing(
        /* TODO enable stream if timing changed */
        /* TODO unblank stream if DP */
 
-       if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
-               if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
+       if (dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) {
+               if (pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable)
                        pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg);
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 8d1a1cc94a8b372ffe2918558cf817c6a9023f55..555c1c484cfddcbe1d91e806d88a846ae5e3fc9d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -853,7 +853,7 @@ bool dp_set_test_pattern(
                                CRTC_STATE_VACTIVE);
 
                if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
-                       if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
+                       if (should_use_dmub_lock(pipe_ctx->stream->link)) {
                                union dmub_hw_lock_flags hw_locks = { 0 };
                                struct dmub_hw_lock_inst_flags inst_flags = { 0 };