crypto: qat - refactor compression template logic

The logic that generates the compression templates, which are used by to
submit compression requests to the QAT device, is very similar between
QAT devices and diverges mainly on the HW generation-specific
configuration word.

This makes the logic that generates the compression and decompression
templates common between GEN2 and GEN4 devices and abstracts the
generation-specific logic to the generation-specific implementations.

The adf_gen2_dc.c and adf_gen4_dc.c have been replaced by adf_dc.c, and
the generation-specific logic has been reduced and moved to
adf_gen2_hw_data.c and adf_gen4_hw_data.c.

This does not introduce any functional change.

Co-developed-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com>
Signed-off-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
index 5817b31641856f03b47db776fa8f84d4e9ad8802..7c3c0f561c956203c03f599bc3829a5555b05ddc 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
@@ -9,7 +9,6 @@
 #include <adf_common_drv.h>
 #include <adf_fw_config.h>
 #include <adf_gen4_config.h>
-#include <adf_gen4_dc.h>
 #include <adf_gen4_hw_csr_data.h>
 #include <adf_gen4_hw_data.h>
 #include <adf_gen4_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
index 2d89d4a3a7b9d9404a4e35a9e584087cdb689e24..bd0b1b1015c069173d2789f5f983d693d92119d7 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -9,7 +9,6 @@
 #include <adf_common_drv.h>
 #include <adf_fw_config.h>
 #include <adf_gen4_config.h>
-#include <adf_gen4_dc.h>
 #include <adf_gen4_hw_csr_data.h>
 #include <adf_gen4_hw_data.h>
 #include <adf_gen4_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
index 9425af26d34c06f2a070191f020078c447c05c59..07f2c42a68f5233b8be64eec171424da165977e9 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
@@ -5,7 +5,6 @@
 #include <adf_clock.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c b/drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
index f73d9a4a9ab73ecdfb4ff3d62093b99037bb8cbb..db3c33fa188194c5e59a29740e41c6c7e9d2cb35 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
@@ -3,7 +3,6 @@
 #include <adf_accel_devices.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
index 1a2f36b603fbf4a9ec8fe533d1e2e05d76f457b7..0b410b41474d82a6ea1a30c2a73dbcc783f78afe 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
@@ -5,7 +5,6 @@
 #include <adf_clock.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c b/drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
index 29e53b41a8959254ad783532af01b672f353f089..7f00035d3661b7f9a79692d33ebf77da8a7f341e 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
@@ -3,7 +3,6 @@
 #include <adf_accel_devices.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_common/Makefile b/drivers/crypto/intel/qat/qat_common/Makefile
index 0370eaad42b113e66c1673f1814022c7d088a4be..0a9da7398a780ee33a1faa4aa242461f22365336 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/Makefile
+++ b/drivers/crypto/intel/qat/qat_common/Makefile
@@ -8,13 +8,12 @@ intel_qat-y := adf_accel_engine.o \
        adf_cfg_services.o \
        adf_clock.o \
        adf_ctl_drv.o \
+       adf_dc.o \
        adf_dev_mgr.o \
        adf_gen2_config.o \
-       adf_gen2_dc.o \
        adf_gen2_hw_csr_data.o \
        adf_gen2_hw_data.o \
        adf_gen4_config.o \
-       adf_gen4_dc.o \
        adf_gen4_hw_csr_data.o \
        adf_gen4_hw_data.o \
        adf_gen4_pm.o \

diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
index 1e301a20c2445fc69498542ee19396a956d48629..a39f506322f678440f15524d921330be784fcfd8 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
@@ -12,6 +12,7 @@
 #include <linux/qat/qat_mig_dev.h>
 #include <linux/wordpart.h>
 #include "adf_cfg_common.h"
+#include "adf_dc.h"
 #include "adf_rl.h"
 #include "adf_telemetry.h"
 #include "adf_pfvf_msg.h"
@@ -267,7 +268,8 @@ struct adf_pfvf_ops {
 };
 
 struct adf_dc_ops {
-       void (*build_deflate_ctx)(void *ctx);
+       int (*build_comp_block)(void *ctx, enum adf_dc_algo algo);
+       int (*build_decomp_block)(void *ctx, enum adf_dc_algo algo);
 };
 
 struct qat_migdev_ops {

diff --git a/drivers/crypto/intel/qat/qat_common/adf_dc.c b/drivers/crypto/intel/qat/qat_common/adf_dc.c
new file mode 100644 (file)
index 0000000..4beb4b7
--- /dev/null
+++ b/drivers/crypto/intel/qat/qat_common/adf_dc.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2022 Intel Corporation */
+#include "adf_accel_devices.h"
+#include "adf_dc.h"
+#include "icp_qat_fw_comp.h"
+
+int qat_comp_build_ctx(struct adf_accel_dev *accel_dev, void *ctx, enum adf_dc_algo algo)
+{
+       struct icp_qat_fw_comp_req *req_tmpl = ctx;
+       struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
+       struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
+       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+       int ret;
+
+       memset(req_tmpl, 0, sizeof(*req_tmpl));
+       header->hdr_flags =
+               ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+       header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
+       header->comn_req_flags =
+               ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
+                                           QAT_COMN_PTR_TYPE_SGL);
+       header->serv_specif_flags =
+               ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
+                                           ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
+                                           ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
+                                           ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
+                                           ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
+
+       /* Build HW config block for compression */
+       ret = GET_DC_OPS(accel_dev)->build_comp_block(ctx, algo);
+       if (ret) {
+               dev_err(&GET_DEV(accel_dev), "Failed to build compression block\n");
+               return ret;
+       }
+
+       req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
+       req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
+       req_pars->req_par_flags =
+               ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
+                                                     ICP_QAT_FW_COMP_EOP,
+                                                     ICP_QAT_FW_COMP_BFINAL,
+                                                     ICP_QAT_FW_COMP_CNV,
+                                                     ICP_QAT_FW_COMP_CNV_RECOVERY,
+                                                     ICP_QAT_FW_COMP_NO_CNV_DFX,
+                                                     ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
+                                                     ICP_QAT_FW_COMP_NO_XXHASH_ACC,
+                                                     ICP_QAT_FW_COMP_CNV_ERROR_NONE,
+                                                     ICP_QAT_FW_COMP_NO_APPEND_CRC,
+                                                     ICP_QAT_FW_COMP_NO_DROP_DATA);
+       ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
+       ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP);
+
+       /* Fill second half of the template for decompression */
+       memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
+       req_tmpl++;
+
+       /* Build HW config block for decompression */
+       ret = GET_DC_OPS(accel_dev)->build_decomp_block(req_tmpl, algo);
+       if (ret)
+               dev_err(&GET_DEV(accel_dev), "Failed to build decompression block\n");
+
+       return ret;
+}

diff --git a/drivers/crypto/intel/qat/qat_common/adf_dc.h b/drivers/crypto/intel/qat/qat_common/adf_dc.h
new file mode 100644 (file)
index 0000000..6cb5e09
--- /dev/null
+++ b/drivers/crypto/intel/qat/qat_common/adf_dc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright(c) 2025 Intel Corporation */
+#ifndef ADF_DC_H
+#define ADF_DC_H
+
+struct adf_accel_dev;
+
+enum adf_dc_algo {
+       QAT_DEFLATE,
+       QAT_LZ4,
+       QAT_LZ4S,
+       QAT_ZSTD,
+};
+
+int qat_comp_build_ctx(struct adf_accel_dev *accel_dev, void *ctx, enum adf_dc_algo algo);
+
+#endif /* ADF_DC_H */

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.c b/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.c
deleted file mode 100644 (file)
index 47261b1..0000000
--- a/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright(c) 2022 Intel Corporation */
-#include "adf_accel_devices.h"
-#include "adf_gen2_dc.h"
-#include "icp_qat_fw_comp.h"
-
-static void qat_comp_build_deflate_ctx(void *ctx)
-{
-       struct icp_qat_fw_comp_req *req_tmpl = (struct icp_qat_fw_comp_req *)ctx;
-       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
-       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
-       struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
-       struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
-
-       memset(req_tmpl, 0, sizeof(*req_tmpl));
-       header->hdr_flags =
-               ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
-       header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
-       header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
-       header->comn_req_flags =
-               ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
-                                           QAT_COMN_PTR_TYPE_SGL);
-       header->serv_specif_flags =
-               ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
-                                           ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
-       cd_pars->u.sl.comp_slice_cfg_word[0] =
-               ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
-                                                   ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
-                                                   ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
-                                                   ICP_QAT_HW_COMPRESSION_DEPTH_1,
-                                                   ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
-       req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
-       req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
-       req_pars->req_par_flags =
-               ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
-                                                     ICP_QAT_FW_COMP_EOP,
-                                                     ICP_QAT_FW_COMP_BFINAL,
-                                                     ICP_QAT_FW_COMP_CNV,
-                                                     ICP_QAT_FW_COMP_CNV_RECOVERY,
-                                                     ICP_QAT_FW_COMP_NO_CNV_DFX,
-                                                     ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
-                                                     ICP_QAT_FW_COMP_NO_XXHASH_ACC,
-                                                     ICP_QAT_FW_COMP_CNV_ERROR_NONE,
-                                                     ICP_QAT_FW_COMP_NO_APPEND_CRC,
-                                                     ICP_QAT_FW_COMP_NO_DROP_DATA);
-       ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
-       ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP);
-
-       /* Fill second half of the template for decompression */
-       memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
-       req_tmpl++;
-       header = &req_tmpl->comn_hdr;
-       header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
-       cd_pars = &req_tmpl->cd_pars;
-       cd_pars->u.sl.comp_slice_cfg_word[0] =
-               ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
-                                                   ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
-                                                   ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
-                                                   ICP_QAT_HW_COMPRESSION_DEPTH_1,
-                                                   ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
-}
-
-void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
-{
-       dc_ops->build_deflate_ctx = qat_comp_build_deflate_ctx;
-}
-EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.h b/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.h
deleted file mode 100644 (file)
index 6eae023..0000000
--- a/drivers/crypto/intel/qat/qat_common/adf_gen2_dc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright(c) 2022 Intel Corporation */
-#ifndef ADF_GEN2_DC_H
-#define ADF_GEN2_DC_H
-
-#include "adf_accel_devices.h"
-
-void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops);
-
-#endif /* ADF_GEN2_DC_H */

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
index 2b263442c85658a871fed0957c5a7781287333b3..6a505e9a5cf9d148c2158c818908a771d0a5ebf4 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
@@ -1,7 +1,9 @@
 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
 /* Copyright(c) 2020 Intel Corporation */
 #include "adf_common_drv.h"
+#include "adf_dc.h"
 #include "adf_gen2_hw_data.h"
+#include "icp_qat_fw_comp.h"
 #include "icp_qat_hw.h"
 #include <linux/pci.h>
 
@@ -169,3 +171,58 @@ void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
        }
 }
 EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);
+
+static int adf_gen2_build_comp_block(void *ctx, enum adf_dc_algo algo)
+{
+       struct icp_qat_fw_comp_req *req_tmpl = ctx;
+       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+
+       switch (algo) {
+       case QAT_DEFLATE:
+               header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       cd_pars->u.sl.comp_slice_cfg_word[0] =
+               ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
+                                                   ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
+                                                   ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
+                                                   ICP_QAT_HW_COMPRESSION_DEPTH_1,
+                                                   ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+       return 0;
+}
+
+static int adf_gen2_build_decomp_block(void *ctx, enum adf_dc_algo algo)
+{
+       struct icp_qat_fw_comp_req *req_tmpl = ctx;
+       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+
+       switch (algo) {
+       case QAT_DEFLATE:
+               header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+       break;
+       default:
+               return -EINVAL;
+       }
+
+       cd_pars->u.sl.comp_slice_cfg_word[0] =
+               ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
+                                                   ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
+                                                   ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
+                                                   ICP_QAT_HW_COMPRESSION_DEPTH_1,
+                                                   ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
+
+       return 0;
+}
+
+void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
+{
+       dc_ops->build_comp_block = adf_gen2_build_comp_block;
+       dc_ops->build_decomp_block = adf_gen2_build_decomp_block;
+}
+EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
index 708e9186127bbdf3db4c8e602f8b6af993a3d927..59bad368a921ec6d1f504c85eaaae7f3e3a9ed78 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
@@ -88,5 +88,6 @@ void adf_gen2_get_arb_info(struct arb_info *arb_info);
 void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev);
 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev);
 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
+void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops);
 
 #endif

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.c
deleted file mode 100644 (file)
index 5859238..0000000
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.c
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright(c) 2022 Intel Corporation */
-#include "adf_accel_devices.h"
-#include "icp_qat_fw_comp.h"
-#include "icp_qat_hw_20_comp.h"
-#include "adf_gen4_dc.h"
-
-static void qat_comp_build_deflate(void *ctx)
-{
-       struct icp_qat_fw_comp_req *req_tmpl =
-                               (struct icp_qat_fw_comp_req *)ctx;
-       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
-       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
-       struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
-       struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = {0};
-       struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = {0};
-       struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = {0};
-       u32 upper_val;
-       u32 lower_val;
-
-       memset(req_tmpl, 0, sizeof(*req_tmpl));
-       header->hdr_flags =
-               ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
-       header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
-       header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
-       header->comn_req_flags =
-               ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
-                                           QAT_COMN_PTR_TYPE_SGL);
-       header->serv_specif_flags =
-               ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
-                                           ICP_QAT_FW_COMP_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
-                                           ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
-       hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
-       hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
-       hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
-       hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
-       hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
-       hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
-       hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
-       hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
-
-       upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
-       lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
-
-       cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
-       cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
-
-       req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
-       req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
-       req_pars->req_par_flags =
-               ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
-                                                     ICP_QAT_FW_COMP_EOP,
-                                                     ICP_QAT_FW_COMP_BFINAL,
-                                                     ICP_QAT_FW_COMP_CNV,
-                                                     ICP_QAT_FW_COMP_CNV_RECOVERY,
-                                                     ICP_QAT_FW_COMP_NO_CNV_DFX,
-                                                     ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
-                                                     ICP_QAT_FW_COMP_NO_XXHASH_ACC,
-                                                     ICP_QAT_FW_COMP_CNV_ERROR_NONE,
-                                                     ICP_QAT_FW_COMP_NO_APPEND_CRC,
-                                                     ICP_QAT_FW_COMP_NO_DROP_DATA);
-
-       /* Fill second half of the template for decompression */
-       memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
-       req_tmpl++;
-       header = &req_tmpl->comn_hdr;
-       header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
-       cd_pars = &req_tmpl->cd_pars;
-
-       hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
-       lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
-
-       cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
-       cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
-}
-
-void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
-{
-       dc_ops->build_deflate_ctx = qat_comp_build_deflate;
-}
-EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.h
deleted file mode 100644 (file)
index 0b1a677..0000000
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_dc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright(c) 2022 Intel Corporation */
-#ifndef ADF_GEN4_DC_H
-#define ADF_GEN4_DC_H
-
-#include "adf_accel_devices.h"
-
-void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
-
-#endif /* ADF_GEN4_DC_H */

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
index 099949a2421c0fab7c5445591cc5b8fd4b07cd3e..0406cb09c5bbb91c69498b0b077804a09558f1cf 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
@@ -9,6 +9,8 @@
 #include "adf_fw_config.h"
 #include "adf_gen4_hw_data.h"
 #include "adf_gen4_pm.h"
+#include "icp_qat_fw_comp.h"
+#include "icp_qat_hw_20_comp.h"
 
 u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)
 {
@@ -663,3 +665,71 @@ int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number
        return ret;
 }
 EXPORT_SYMBOL_GPL(adf_gen4_bank_state_restore);
+
+static int adf_gen4_build_comp_block(void *ctx, enum adf_dc_algo algo)
+{
+       struct icp_qat_fw_comp_req *req_tmpl = ctx;
+       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+       struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = { };
+       struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = { };
+       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+       u32 upper_val;
+       u32 lower_val;
+
+       switch (algo) {
+       case QAT_DEFLATE:
+               header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
+       hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
+       hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
+       hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
+       hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
+       hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
+       hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
+       hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
+
+       upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
+       lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
+
+       cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
+       cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
+
+       return 0;
+}
+
+static int adf_gen4_build_decomp_block(void *ctx, enum adf_dc_algo algo)
+{
+       struct icp_qat_fw_comp_req *req_tmpl = ctx;
+       struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = { };
+       struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
+       struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
+       u32 lower_val;
+
+       switch (algo) {
+       case QAT_DEFLATE:
+               header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
+       lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
+
+       cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
+       cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
+
+       return 0;
+}
+
+void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
+{
+       dc_ops->build_comp_block = adf_gen4_build_comp_block;
+       dc_ops->build_decomp_block = adf_gen4_build_decomp_block;
+}
+EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
index 51fc2eaa263ec06968772d0bf313c9cadb5ae494..e4f4d5fa616deb3eb2c6cf3b482de4aa8090d285 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
@@ -7,6 +7,7 @@
 
 #include "adf_accel_devices.h"
 #include "adf_cfg_common.h"
+#include "adf_dc.h"
 
 /* PCIe configuration space */
 #define ADF_GEN4_BAR_MASK      (BIT(0) | BIT(2) | BIT(4))
@@ -180,5 +181,6 @@ int adf_gen4_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
 int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev,
                                u32 bank_number, struct bank_state *state);
 bool adf_gen4_services_supported(unsigned long service_mask);
+void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
 
 #endif

diff --git a/drivers/crypto/intel/qat/qat_common/qat_comp_algs.c b/drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
index a0a29b97a749500cba8420b08432588c80280eb7..8b123472b71cc49e1a1b902f3b0bd06ccd973f39 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
+++ b/drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
@@ -8,6 +8,7 @@
 #include <linux/workqueue.h>
 #include "adf_accel_devices.h"
 #include "adf_common_drv.h"
+#include "adf_dc.h"
 #include "qat_bl.h"
 #include "qat_comp_req.h"
 #include "qat_compression.h"
@@ -145,9 +146,7 @@ static int qat_comp_alg_init_tfm(struct crypto_acomp *acomp_tfm)
                return -EINVAL;
        ctx->inst = inst;
 
-       ctx->inst->build_deflate_ctx(ctx->comp_ctx);
-
-       return 0;
+       return qat_comp_build_ctx(inst->accel_dev, ctx->comp_ctx, QAT_DEFLATE);
 }
 
 static void qat_comp_alg_exit_tfm(struct crypto_acomp *acomp_tfm)

diff --git a/drivers/crypto/intel/qat/qat_common/qat_compression.c b/drivers/crypto/intel/qat/qat_common/qat_compression.c
index 7842a9f22178c2c0dcb6ce56da1cd36fa8449a31..c285b45b8679da2a7c3ba5bd4239290363f0d33b 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/qat_compression.c
+++ b/drivers/crypto/intel/qat/qat_common/qat_compression.c
@@ -144,7 +144,6 @@ static int qat_compression_create_instances(struct adf_accel_dev *accel_dev)
                inst->id = i;
                atomic_set(&inst->refctr, 0);
                inst->accel_dev = accel_dev;
-               inst->build_deflate_ctx = GET_DC_OPS(accel_dev)->build_deflate_ctx;
 
                snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);
                ret = adf_cfg_get_param_value(accel_dev, SEC, key, val);

diff --git a/drivers/crypto/intel/qat/qat_common/qat_compression.h b/drivers/crypto/intel/qat/qat_common/qat_compression.h
index aebac2302dcf23a9af5e1eafdb55c50c8959e8e8..5ced3ed0e5eaea81f455ed4a2451ce39bb9e4199 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/qat_compression.h
+++ b/drivers/crypto/intel/qat/qat_common/qat_compression.h
@@ -20,7 +20,6 @@ struct qat_compression_instance {
        atomic_t refctr;
        struct qat_instance_backlog backlog;
        struct adf_dc_data *dc_data;
-       void (*build_deflate_ctx)(void *ctx);
 };
 
 static inline bool adf_hw_dev_has_compression(struct adf_accel_dev *accel_dev)

diff --git a/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index bf9e8f34f451e35ad887c20013444f56c2050afe..5b4bd0ba1ccbe6438736d12675292c1f7a38b97d 100644 (file)
--- a/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -4,7 +4,6 @@
 #include <adf_admin.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>

diff --git a/drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c b/drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
index bc59c1473eefabe300b8b2a8959719b16be62bc5..828456c43b760cca3079a7467e8f824c08941feb 100644 (file)
--- a/drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
@@ -3,7 +3,6 @@
 #include <adf_accel_devices.h>
 #include <adf_common_drv.h>
 #include <adf_gen2_config.h>
-#include <adf_gen2_dc.h>
 #include <adf_gen2_hw_csr_data.h>
 #include <adf_gen2_hw_data.h>
 #include <adf_gen2_pfvf.h>