drm/i915: pass dev_priv explicitly to PSR_EVENT

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR_EVENT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 156660ab7adffc270d4c8763c73a58df8c69dc87..2dca9957a06b9a7d3fb8769d3e48d28606948318 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -415,7 +415,9 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
                if (DISPLAY_VER(dev_priv) >= 9) {
                        u32 val;
 
-                       val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
+                       val = intel_de_rmw(dev_priv,
+                                          PSR_EVENT(dev_priv, cpu_transcoder),
+                                          0, 0);
 
                        psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
                }

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 785e4f9e78284ef2199e23bc50eaba85f320c4be..817bc372bf357d24e351b630431356170caee317 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -195,7 +195,7 @@
 #define _PSR_EVENT_TRANS_C                     0x62848
 #define _PSR_EVENT_TRANS_D                     0x63848
 #define _PSR_EVENT_TRANS_EDP                   0x6f848
-#define PSR_EVENT(tran)                                _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
+#define PSR_EVENT(dev_priv, tran)                              _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE                REG_BIT(17)
 #define  PSR_EVENT_PSR2_DISABLED               REG_BIT(16)
 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN      REG_BIT(15)