drm/amdgpu: Per-instance init func for JPEG2_5_0

Add helper functions to handle per-instance initialization
and deinitialization in JPEG2_5_0.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index b19724928ce4a9273b5688e5d051a3241c9d0146..0490b672d8d31ed53eb65d8073a3e571ccc93df6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -330,6 +330,44 @@ static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
        WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
 }
 
+static void jpeg_v2_5_start_inst(struct amdgpu_device *adev, int i)
+{
+       struct amdgpu_ring *ring = adev->jpeg.inst[i].ring_dec;
+       /* disable anti hang mechanism */
+       WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
+               ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+
+       /* JPEG disable CGC */
+       jpeg_v2_5_disable_clock_gating(adev, i);
+
+       /* MJPEG global tiling registers */
+       WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config);
+       WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config);
+
+       /* enable JMI channel */
+       WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
+               ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+
+       /* enable System Interrupt for JRBC */
+       WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
+               JPEG_SYS_INT_EN__DJRBC_MASK,
+               ~JPEG_SYS_INT_EN__DJRBC_MASK);
+
+       WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
+       WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
+       WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
+               lower_32_bits(ring->gpu_addr));
+       WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
+               upper_32_bits(ring->gpu_addr));
+       WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
+       WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
+       WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
+       WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
+       ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
+}
+
 /**
  * jpeg_v2_5_start - start JPEG block
  *
@@ -339,52 +377,33 @@ static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
  */
 static int jpeg_v2_5_start(struct amdgpu_device *adev)
 {
-       struct amdgpu_ring *ring;
        int i;
 
        for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
                if (adev->jpeg.harvest_config & (1 << i))
                        continue;
+               jpeg_v2_5_start_inst(adev, i);
 
-               ring = adev->jpeg.inst[i].ring_dec;
-               /* disable anti hang mechanism */
-               WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
-                       ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
-
-               /* JPEG disable CGC */
-               jpeg_v2_5_disable_clock_gating(adev, i);
-
-               /* MJPEG global tiling registers */
-               WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
-                       adev->gfx.config.gb_addr_config);
-               WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
-                       adev->gfx.config.gb_addr_config);
-
-               /* enable JMI channel */
-               WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
-                       ~UVD_JMI_CNTL__SOFT_RESET_MASK);
-
-               /* enable System Interrupt for JRBC */
-               WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
-                       JPEG_SYS_INT_EN__DJRBC_MASK,
-                       ~JPEG_SYS_INT_EN__DJRBC_MASK);
-
-               WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
-               WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
-               WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
-                       lower_32_bits(ring->gpu_addr));
-               WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
-                       upper_32_bits(ring->gpu_addr));
-               WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
-               WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
-               WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
-               WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
-               ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
        }
 
        return 0;
 }
 
+static void jpeg_v2_5_stop_inst(struct amdgpu_device *adev, int i)
+{
+       /* reset JMI */
+       WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
+               UVD_JMI_CNTL__SOFT_RESET_MASK,
+               ~UVD_JMI_CNTL__SOFT_RESET_MASK);
+
+       jpeg_v2_5_enable_clock_gating(adev, i);
+
+       /* enable anti hang mechanism */
+       WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
+               UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
+               ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+}
+
 /**
  * jpeg_v2_5_stop - stop JPEG block
  *
@@ -399,18 +418,7 @@ static int jpeg_v2_5_stop(struct amdgpu_device *adev)
        for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
                if (adev->jpeg.harvest_config & (1 << i))
                        continue;
-
-               /* reset JMI */
-               WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
-                       UVD_JMI_CNTL__SOFT_RESET_MASK,
-                       ~UVD_JMI_CNTL__SOFT_RESET_MASK);
-
-               jpeg_v2_5_enable_clock_gating(adev, i);
-
-               /* enable anti hang mechanism */
-               WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
-                       UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
-                       ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
+               jpeg_v2_5_stop_inst(adev, i);
        }
 
        return 0;