ARM: socfpga: dts: fix qspi node compatible

The QSPI flash node needs to have the required "jedec,spi-nor" in the
compatible string.

Fixes: 1df99da8953 ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
index 2b645642b9352c13d2d0797d68a2053ec35df597..2a745522404d6b065ef71bbde83e648875d95014 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
@@ -12,7 +12,7 @@
        flash0: n25q00@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00aa";
+               compatible = "micron,mt25qu02g", "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <100000000>;
 

diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 90e676e7019f23377dd05bbf70b45f7af0d47ea5..1b02d46496a852786705a5875e5e5adc20d9540d 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -119,7 +119,7 @@
        flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q256a";
+               compatible = "micron,n25q256a", "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <100000000>;
 

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 6f138b2b26163ada37d0c1cb0462ed70d44a4b4e..51bb436784e241470d7aba219b38323a37357007 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -124,7 +124,7 @@
        flash0: n25q00@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "micron,mt25qu02g", "jedec,spi-nor";
                reg = <0>;      /* chip select */
                spi-max-frequency = <100000000>;
 

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index c155ff02eb6e035a7c7e526635a80a5feda9b4d8..cae9ddd5ed38bbd57efe8371724e59aa49fb0ac2 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -169,7 +169,7 @@
        flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "micron,mt25qu02g", "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <100000000>;
 

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index 8d5d3996f6f27122412d68072767d621fa11ae8f..ca18b959e6559ebdd4515d71877211022559be19 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -80,7 +80,7 @@
        flash: flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q256a";
+               compatible = "micron,n25q256a", "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <100000000>;
                m25p,fast-read;

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 99a71757cdf46330418b65aeae3646668229c378..3f7aa7bf0863aa1150b64ad4a58e120a1bdf7fc1 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -116,7 +116,7 @@
        flash0: n25q512a@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q512a";
+               compatible = "micron,n25q512a", "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <100000000>;
 

diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index a060718758b6755a154c1842f95301d1a8c93806..25874e1b9c82987e090c7229cad34a07edb3c674 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -224,7 +224,7 @@
        n25q128@0 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q128";
+               compatible = "micron,n25q128", "jedec,spi-nor";
                reg = <0>;              /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;
@@ -241,7 +241,7 @@
        n25q00@1 {
                #address-cells = <1>;
                #size-cells = <1>;
-               compatible = "n25q00";
+               compatible = "micron,mt25qu02g", "jedec,spi-nor";
                reg = <1>;              /* chip select */
                spi-max-frequency = <100000000>;
                m25p,fast-read;