drm/amdgpu/hdp4.0: do a posting read when flushing HDP

Need to read back to make sure the write goes through.

Cc: David Belanger <david.belanger@amd.com>
Reviewed-by: Frank Min <frank.min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
index e019249883fb2f026e1efd9c2bcc77e8f8c02e64..194026e9be33311cd415d2f64d683553774a490b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -40,10 +40,12 @@
 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring)
 {
-       if (!ring || !ring->funcs->emit_wreg)
+       if (!ring || !ring->funcs->emit_wreg) {
                WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-       else
+               RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
                amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+       }
 }
 
 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
@@ -54,11 +56,13 @@ static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
            amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
                return;
 
-       if (!ring || !ring->funcs->emit_wreg)
+       if (!ring || !ring->funcs->emit_wreg) {
                WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
-       else
+               RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
+       } else {
                amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
                        HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
+       }
 }
 
 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,