drm/i915: Make the CHV CGM CSC register writes lockless

The CHV CGM CSC registers are single buffered and so we
may have to write them from the vblank worker, which
imposes very tight dealines. Drop the pointless locking
for the register accessess to reduce the overhead.
All the other registers we bash from the vblank worker
(LUTs) were already made lockless earlier.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220202111616.1579-3-ville.syrjala@linux.intel.com
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 66be0349c0c87d756f7953678ee2561f5f9e8515..e94ec57260f1709efd42e0a15cfcb7918f49bdcb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -396,16 +396,16 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
                coeffs[i] |= (abs_coeff >> 20) & 0xfff;
        }
 
-       intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
-                      coeffs[1] << 16 | coeffs[0]);
-       intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
-                      coeffs[3] << 16 | coeffs[2]);
-       intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
-                      coeffs[5] << 16 | coeffs[4]);
-       intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
-                      coeffs[7] << 16 | coeffs[6]);
-       intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
-                      coeffs[8]);
+       intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
+                         coeffs[1] << 16 | coeffs[0]);
+       intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
+                         coeffs[3] << 16 | coeffs[2]);
+       intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
+                         coeffs[5] << 16 | coeffs[4]);
+       intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
+                         coeffs[7] << 16 | coeffs[6]);
+       intel_de_write_fw(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
+                         coeffs[8]);
 }
 
 /* convert hw value with given bit_precision to lut property val */