drm/amd/pm: Add support for reset completion on aldebaran

v1: On aldebaran, after hardware context restore, another handshake
needs to happen with PMFW so that reset recovery is complete from
PMFW side. Treat this as RESET_COMPLETE event for aldebaran.

v2: Cleanup coding style, info logs

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
index 433dd1e9ec4f819a7da73fac7f4d7c609ab7ff0d..610266088ff1c9668fa94a15bb955a3c2b7fbb11 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/aldebaran_ppsmc.h
@@ -100,7 +100,8 @@
 #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x40
 #define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow  0x41
 
-#define PPSMC_Message_Count                      0x42
+#define PPSMC_MSG_GfxDriverResetRecovery       0x42
+#define PPSMC_Message_Count                    0x43
 
 //PPSMC Reset Types
 #define PPSMC_RESET_TYPE_WARM_RESET              0x00

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 5bfb60f41dd422b92d685aea3db2c0a2df1f0c73..89a16dcd0fff90abd2c7bffbd25ab357a1797c23 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -225,6 +225,7 @@
        __SMU_DUMMY_MAP(DisableDeterminism),            \
        __SMU_DUMMY_MAP(SetUclkDpmMode),                \
        __SMU_DUMMY_MAP(LightSBR),                      \
+       __SMU_DUMMY_MAP(GfxDriverResetRecovery),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)  SMU_MSG_##type

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
index 6d4beb343a6c7bfadf3c4a73c8c8760ba752a127..8145e1cbf181eeb87318687920cb6ecd04f6081c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
@@ -268,5 +268,8 @@ int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement);
 
+int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
+                            uint64_t event_arg);
+
 #endif
 #endif

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index ec485308b921199b18b32f5a72304eeb67188dab..472829f5ff1b541f806419e01bf9b6265ee60b1b 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -126,7 +126,8 @@ static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT
        MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
        MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
        MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
-       MSG_MAP(SetUclkDpmMode,                          PPSMC_MSG_SetUclkDpmMode,              0),
+       MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
+       MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 };
 
 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
@@ -1583,6 +1584,7 @@ static const struct pptable_funcs aldebaran_ppt_funcs = {
        .mode1_reset = smu_v13_0_mode1_reset,
        .set_mp1_state = aldebaran_set_mp1_state,
        .mode2_reset = aldebaran_mode2_reset,
+       .wait_for_event = smu_v13_0_wait_for_event,
 };
 
 void aldebaran_set_ppt_funcs(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 8974cd55994b162b8cc04db6568557951f623831..1f860969ea1ceacd093c74f68c51607de4971bd3 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1374,6 +1374,33 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
        return ret;
 }
 
+static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
+                                            uint64_t event_arg)
+{
+       int ret = 0;
+
+       dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
+       ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
+
+       return ret;
+}
+
+int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
+                            uint64_t event_arg)
+{
+       int ret = -EINVAL;
+
+       switch (event) {
+       case SMU_EVENT_RESET_COMPLETE:
+               ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
+               break;
+       default:
+               break;
+       }
+
+       return ret;
+}
+
 int smu_v13_0_mode2_reset(struct smu_context *smu)
 {
        int ret;