drm/amdgpu/soc15: use common nbio callback to set remap offset

This fixes HDP flushes on systems with non-4K pages.

Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 5dc8663a29e95342b0ca6cddf10ff26f3f1a4f3e..34180c6070dd2bcbe339a3a995ea1271d5f6fe33 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -276,10 +276,6 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 
        if (def != data)
                WREG32_PCIE(smnPCIE_CI_CNTL, data);
-
-       if (amdgpu_sriov_vf(adev))
-               adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
-                       mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
 }
 
 #ifdef CONFIG_PCIEASPM

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 3dd743ebbc02d4e0e906d020cbd7972426053e79..b1b57dcc5a7370453c0ed642d862fa93b73611ce 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -273,9 +273,6 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
 
 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 {
-       if (amdgpu_sriov_vf(adev))
-               adev->rmmio_remap.reg_offset =
-                       SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
 }
 
 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index b684eb519d2a92b5ea125c0429e3e6f0bb75e4a3..fe18df10daaa34babe1662ec1864a2cee97525c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -343,10 +343,6 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 {
        uint32_t baco_cntl;
 
-       if (amdgpu_sriov_vf(adev))
-               adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
-                       mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
-
        if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) &&
            !amdgpu_sriov_vf(adev)) {
                baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index c2e78294c4fdcf16f84982a4fb41e5d6e83f2b7c..d1bd79bbae532facedf9d2534008d8d8ce20d7bb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -422,12 +422,6 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
        u32 inst_mask;
        int i;
 
-       if (amdgpu_sriov_vf(adev))
-               adev->rmmio_remap.reg_offset =
-                       SOC15_REG_OFFSET(
-                               NBIO, 0,
-                               regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
-                       << 2;
        WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
                0xff & ~(adev->gfx.xcc_mask));
 

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8806f54df8bb9a16c70ce4d4b4b5c30ad7ab8055..8d16dacdc172036ac34dcf3f24ae72a6451a94f7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -931,13 +931,9 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
 
 static int soc15_common_early_init(void *handle)
 {
-#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       if (!amdgpu_sriov_vf(adev)) {
-               adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
-               adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
-       }
+       adev->nbio.funcs->set_reg_remap(adev);
        adev->smc_rreg = NULL;
        adev->smc_wreg = NULL;
        adev->pcie_rreg = &amdgpu_device_indirect_rreg;
@@ -1188,11 +1184,6 @@ static int soc15_common_early_init(void *handle)
                        AMD_PG_SUPPORT_JPEG;
                /*TODO: need a new external_rev_id for GC 9.4.4? */
                adev->external_rev_id = adev->rev_id + 0x46;
-               /* GC 9.4.3 uses MMIO register region hole at a different offset */
-               if (!amdgpu_sriov_vf(adev)) {
-                       adev->rmmio_remap.reg_offset = 0x1A000;
-                       adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000;
-               }
                break;
        default:
                /* FIXME: not supported yet */