drm/i915/dp: Account for channel coding efficiency on UHBR links

Apply the correct BW allocation overhead and channel coding efficiency
on UHBR link rates, similarly to DP1.4 link rates.

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 625b1ba93229d8e27791e15d644b2a67e694d595..dd8ac647fe0eac45befae995645f978b706d130e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2397,16 +2397,6 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
        int ch_coding_efficiency =
                drm_dp_bw_channel_coding_efficiency(is_uhbr);
 
-       /*
-        * TODO: adjust for actual UHBR channel coding efficiency and BW
-        * overhead.
-        */
-       if (is_uhbr) {
-               *data_m = pixel_data_rate;
-               *data_n = link_data_rate * 8 / 10;
-               return;
-       }
-
        *data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead),
                                   1000000);
        *data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency),