ARM: dts: rockchip: add clocks in iommu nodes
authorJeffy Chen <jeffy.chen@rock-chips.com>
Fri, 23 Mar 2018 07:38:07 +0000 (15:38 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 16 Apr 2018 12:13:04 +0000 (14:13 +0200)
Add clocks in iommu nodes, since we are going to control clocks in
rockchip iommu driver.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/rk322x.dtsi
arch/arm/boot/dts/rk3288.dtsi

index a97458112ff6e80ca198fe1377521372973e8ca4..567a6a725f9cc889ce19a81aad4b8dbb24bb96bb 100644 (file)
                reg = <0x10118300 0x100>;
                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
index df1e478586753ccbd9cf889108466e45d200f2a4..be80e9a2c9af16fbf10e9cb6ee143a4f0d3151c7 100644 (file)
                reg = <0x20020800 0x100>;
                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+               clock-names = "aclk", "iface";
                iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x20030480 0x40>, <0x200304c0 0x40>;
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vdec_mmu";
+               clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+               clock-names = "aclk", "iface";
                iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x20053f00 0x100>;
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+               clock-names = "aclk", "iface";
                iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x20070800 0x100>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "iep_mmu";
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk", "iface";
                iommu-cells = <0>;
                status = "disabled";
        };
index be9acb6d28a1629e623c874b3956b183e62fc9a0..d7e49d29ace540fe4022b8822b84840ebdb5b65a 100644 (file)
                reg = <0x0 0xff900800 0x0 0x40>;
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "iep_mmu";
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "isp_mmu";
+               clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                rockchip,disable-mmu-reset;
                status = "disabled";
                reg = <0x0 0xff930300 0x0 0x100>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopb_mmu";
+               clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+               clock-names = "aclk", "iface";
                power-domains = <&power RK3288_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
                reg = <0x0 0xff940300 0x0 0x100>;
                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vopl_mmu";
+               clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+               clock-names = "aclk", "iface";
                power-domains = <&power RK3288_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
                reg = <0x0 0xff9a0800 0x0 0x100>;
                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vpu_mmu";
+               clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };
                reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "hevc_mmu";
+               clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
+               clock-names = "aclk", "iface";
                #iommu-cells = <0>;
                status = "disabled";
        };